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Digital pulse generator using leading and trailing edge placement
| Details |
Inventors: Lueker, Jonathan; Hengeveld, John; Needham, Brad; Price, Burt; Schlegel, Jim; Sedeh, Mehrab;
Assignee: Tektronix, Inc. (Wilsonville, OR)
Primary Examiner: Yusko; Donald J.
Assistant Examiner: Giust; John E.
Attorney, Agent or Firm: Smith-Hill; John, Griffith; Boulden G.
A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included. This architecture provides controllable tolerances, permits accurate positioning of a trigger out signal relative to any pulse produced, allows the user to specify the trailing edge timing directly, and permits both pulse width and phase to be specified as a percentage of the overall period and automatically kept proportional when the frequency is varied. It allows synchronized operation of different channels at rates related by powers-of-two, and permits disabling of a channel at an operator determined voltage level. A means for determining, by the use of an external signal, when bursts of pulses synchronized to an external frequency source will begin, is also provided. |
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DETAILED DESCRIPTION Accordingly, it is the object of the present invention to provide a pulse generator with a unique digital architecture that produces more controllable tolerances, especially channel-to-channel tolerances, that can accurately position a trigger out signal relative to any pulse that it produces, that allows the user to specify the trailing edge timing directly, that permits both pulse width and phase to be specified as a percentage of the overall period and the pulse generator then automatically keeps the width proportional and its phase constant when the frequency is varied, that provides a means for controlling, by the use of an external signal, when bursts of pulses synchronized to an external frequency source will begin, that allows some channels to run at half the rate of the others, but synchronized with them, that permits the operator to disable a channel, but have it maintain a dc voltage output at an operator determined level, and that is automatically self-calibrating, only requiring the operator to connect the output to a calibration input to accomplish the calibration.
In a preferred embodiment, the present invention includes a triggerable voltage controlled oscillator (VCO) with two sources of frequency control voltage, an internal DAC and a phase frequency comparison with an external timebase.
In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers".
In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two.
The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta.
The edge locations are then adjusted with slivers and verniers, as in the top octave.
An on-board high quality frequency counter and long time constant A/D converter, as well as a calibration input with a precisely fixed in time threshold detector, permits automatic self-calibration
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