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Five-level switched-capacitor DAC, method of operation thereof and sigma-delta converter employing the same
| Details |
Inventors: Ju, Peicheng; Nagaraj, Krishnaswamy;
Assignee: Lucent Technologies, Inc. (Murray Hill, NJ)
Primary Examiner: Young; Brian
Assistant Examiner: Wamsley; Patrick
Attorney, Agent or Firm:
A digital-to-analog converter (DAC) and a method of converting digital numbers to analog equivalents. In one embodiment, the DAC includes: (1) a data decoder that receives a digital number and an input clock signal and develops therefrom SIGN and M control signals and complementary .phi..sub.1 and .phi..sub.2 clock signals and (2) a conversion circuit, coupled to the data decoder and including first and second operational amplifiers (op amps), a switching circuit and sampling and integrating capacitors, the switching circuit coupling positive and negative reference voltages to the sampling capacitors as a function of states of the SIGN and M control signals and adjusting feedback loops associated with the first and second op amps as a function of states of the .phi..sub.1 and .phi..sub.2 clock signals, the first and second op amps generating a voltage difference at outputs thereof representing an analog equivalent of the digital number. |
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DETAILED DESCRIPTION To address the above-discussed deficiencies of the prior art, the present invention provides a DAC and a method of converting digital numbers to analog equivalents.
In one embodiment, the DAC includes: (1) a data decoder that receives a digital number and an input clock signal and develops therefrom SIGN (and, in one embodiment SIGN) and M (which may be, for instance, M.
sub.
1, M.
sub.
2, and M.
sub.
0) control signals and complementary non-overlapping .
phi.
.
sub.
1 and .
phi.
.
sub.
2 clock signals and (2) a differential switched-capacitor integrator and three reference voltages (positive, negative and ground), that under the control of the signals generated by the data decoder, produces an output voltage thereof representing an analog equivalent of the input digital number.
The present invention introduces a DAC having extremely high (perhaps as high as 16 bit) linearity and fast conversion rate (as fast as the input clock rate).
The positive reference voltage, V.
sub.
RP, and the negative reference voltage, V.
sub.
RN, have the same amplitude but opposite polarity referenced to the ground.
For example, V.
sub.
RP =-V.
sub.
RN =V.
sub.
R Volt, where V.
sub.
R is the reference voltage value.
In one embodiment of the present invention, the input digital number is three bits long in two's complement format.
Only five of the eight possible values represented by the three-bit number are used, corresponding to -2, -1, 0, 1, and 2.
The equivalent analog output voltages are -V.
sub.
R, -1/2V.
sub.
R, 0, +1/2V.
sub.
R and +V.
sub.
R, respectively.
In one embodiment of the present invention, the differential switched-capacitor integrator further includes two single-ended switched-capacitor integrators, each of which includes an operational amplifier (op amp), a sampling capacitor, an integrating capacitor, and a switching circuit.
In each single-ended switched-capacitor integrator, one terminal of the sampling capacitor is always connected to the inverting input terminal of the op amp in the same integrator
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