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 High frequency voltage comparator circuit

Details
Inventors: Iida, Tetsuya;
Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Kawasaki, JP)
Primary Examiner: Anagnos; Larry N.
Assistant Examiner:
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner

A voltage comparator circuit that is useful in A/D converters and D/A converters. The circuit comprises a comparison capacitor, a holding capacitor and input switching transistors. The holding capacitor holds the comparison voltage applied to it from the input switching transistors through the comparison capacitor. Therefore, the circuit can perform accurate voltage comparison even if the input voltages are sampled at a high sampling frequency.

DETAILED DESCRIPTION It is therefore an object of the present invention to provide a voltage comparator circuit which can accurately compare input voltages, obtaining a sufficiently large voltage gain, even if a sampling clock signal of high frequency is used.
The voltage comparator circuit according to the present invention comprises first and second transistor switching means whose current paths receive at one end first and second input voltages, respectively, and are connected at the other end to each other to define a first node and whose gates receive first and second clock signals, respectively, said first and second transistor switching means alternately delivering the first and second input voltage to said first node in synchronism with the first and second clock signals, respectively; generating means including an operating point voltage generator and third transistor switching means whose current path is connected between said operating point voltage generator and a first capacitive element connected to said first node, and which delivers an operating point voltage from said operating point voltage generator to said first capacitive element in synchronism with said first clock signal; and holding means including a second capacitive element and a fourth transistor switching means whose gate is to receive said second clock signal and whose current path is connected between said second capacitive element and a second node where said third transistor switching means is connected to said first capacitive element, said holding means being designed to hold the difference between said first and second input voltages and to apply the same to amplifying means in synchronism with said second clock signal.
The comparator circuit of the invention can amplify the difference between two input voltages and can also hold the amplified difference voltage.
Its output voltage can therefore have an ideal curve even if a sampling clock signal of high frequency is used.
The low frequency voltage gain of the comparator circuit can thus be maintained



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