Low voltage analog-to-digital converters with internal reference voltage and offset

DETAILED DESCRIPTION The present application defines an A-to-D converter system that provides an efficient solution to the problem of supplying the reference voltage.
In one aspect, the solution considers implementation of the A-to-D converter in compact micro-power level circuits.
For example, an array of A-to-D converters is used in CMOS image sensors.
These sensors can include active pixel sensors (APS) and charge-coupled devices (CCD).
The image sensor is arranged into an array of column pixels and row pixels.
Each pixel collects electrical charge when exposed to is light.
Control signals provided to the pixels periodically enable the controllers to transfer the collected charge to the array of A-to-D converters.
The collected charge is converted to digital data and stored in the column-parallel latches.
Since the available chip area and power is limited in column parallel circuits, it is advantageous to provide a substantially compact design where the reference voltage uses the existing supply voltage.
Further, by adjusting the total capacitance of the binary-weighted conversion capacitors, the effective reference voltage can be changed.
A schematic diagram of an embodiment of the A-to-D converter system 300 is shown in FIG.
3.
The converter system 300 eliminates the need for the internally-generated or externally-supplied reference voltage 210 by using the rail supply voltage (V.
sub.
DD) 304.
The converter system 300 allows the capacitors 302 to use the existing supply voltage 304 by providing an adjustable reference capacitor (C.
sub.
REF) 308 at the positive input signal node 306.
Initially, the bottom plates of the capacitors 302 are grounded.
During the conversion process, the bottom plates of the capacitors 302 are successively connected to the supply voltage 304.
The adjustable reference capacitor 308 provides additional capacitance at the positive input signal node 306.
Thus, the maximum capacitance at the positive input signal node 306 increases to 2.
sup.
n -1)*C+C.
sub.
REF (2) The least-significant bit (LSB) voltage is equal to ##EQU2## In one example, if the value of C