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Parallel-comparison-type-analog-to-digital-converter

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Parallel comparison type analog to digital converter

Details

Inventors: Fujita, Tsuneo;
Assignee: NEC (Tokyo, JP)
Primary Examiner:
Assistant Examiner:
Attorney, Agent or Firm:

A parallel comparison type A/D converter which can produce a digital output with improved monotonic operation. The A/D converter comprises a plurality of comparators for comparing an analog signal with a plurality comparison voltage, and a plurality of logic gates each having a first input terminal of a positive logic and a second input terminal of a negative logic, one of the first and second input terminals receiving an outpt signal from one of the comparators of a certain weight and the other of the first and second input terminals receiving an output signal from the comparator having a weight subsequent to the certain weight. The threshold values of the first and second input terminals are made different from each other.

DETAILED DESCRIPTION It is an object of the present invention to provide a parallel comparison type A/D converter having improved monotonic operation in A/D conversion characteristics.
It is another object of the present invention to provide a parallel comparison type A/D converter which can be fabricated as a high density structure in a semiconductor integrated circuit.
A parallel comparison type A/D converter according to the present invention comprises an ordered plurality of comparators, each having different weight and comparing an analog signal with a comparison voltage corresponding to its weight, and a plurality of logic gates for determining the closest weight to the analog signal, each of the logic gates having a first input terminal of a positive logic and a second input terminal of a negative logic, the first input terminal receiving an output signal from one of the comparators having a certain weight, and the second input terminal receiving an output signal from the comparator having the subsequent weight to the certain weight, and is featured that threshold values of the first and second input terminals are made different from each other.
According to the present invention, if the comparator generates an output signal of an intermediate value which is not classified into either of two binary logic levels, such an output signal of the intermediate level is necessarily recognized as one of the binary logic signals by at least one of the first and second input terminals.
Accordingly, any problem caused by the output of the intermediate value from the comparator can be effectively avoided.

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