Pipe-lined CCD analog-to-digital converter

DETAILED DESCRIPTION What is claimed is: 1.
An analog-to-digital converter comprising: a plurality, n in number, of CCD comparator structures, each for furnishing a respective output indication of first or second sort depending on whether or not a charge packet input supplied to a first input connection thereof exceeds charge packet inputs respectively supplied second and third input connections thereof, said comparator structures being consecutively ordinally numbered first through n.
sup.
th ; means for generating clock signals having cycles assumed to be consecutively numbered from a reference time for purpose of definition in claiming; means for supplying respective charge packets on each successive clock cycle, descriptive of an analog input signal level on evenly numbered clock cycles and of a zero level on oddly numbered clock cycles; a first pipeline connection for successively admitting on successive clock cycles each of those charge packets to the first input connections of said CCD comparator structures in reverse order of their ordinal numbering; means for supplying to the third input connection of each CCD comparator structure respective charge packets each successive clock cycle, descriptive of a trial bit level on evenly numbered clock cycles and of a zero level on oddly numbered clock cycles, the respective reference levels being related in substantially binary weighting with progressively larger reference levels being applied to CCD comparator structures in said plurality with successively higher numbers; respective means associated with each CCD comparator structure except the first for applying on the succeeding clock cycle the charge packet formerly applied to its second connection to the second input connection of the CCD comparator structure with next lower ordinal numbering; and respective means responsive to each CCD comparator structure except the first furnishing a respective output indication of said first sort for applying on the succeeding clock cycle the charge packet formerly applied to its third input connection to the second input connection of the CCD comparator structure with next lower ordinal number