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 Radar processing apparatus and method

Details
Inventors: Pieronek, James V.; Gertz, Jeffrey L.;
Assignee: Massachusetts Institute of Technology (Cambridge, MA)
Primary Examiner: Sotomayor; John B.
Assistant Examiner:
Attorney, Agent or Firm: Testa, Hurwitz & Thibeault

A radar processor comprises a multi-port memory device having memory which can be accessed by at least three ports. A first port receives input data from a data providing means. A second port couples a first processor which performs radar processing. A third port couples at least one second processor which assists the first processor by also performing radar processing. The multi-port memory device further includes an arbiter for coordinating and determining when each of the three ports can access the memory of the multi-port memory device. The first and second processors share information with each other via the multi-port memory device.

DETAILED DESCRIPTION To address the performance concerns raised by the use of an ASR-9 in an urban airport setting while minimizing the cost associated with achieving the desired performance results, an existing ASR-9 is utilized as a foundation of a new radar surveillance processing system.
The new radar processing system can achieve levels of performance and effectiveness not attainable by a conventional ASR-9.
A surveillance radar processing system according to the invention differs significantly, both structurally and functionally, from a conventional ASR-9.
The new radar processing system includes a multi-port memory device which receives both radar return (i.
e.
, primary return) and beacon reply signals on one port.
The ASR-9's Array Signal Processor (ASP) is coupled to another port, and at least one auxiliary processor is connected to still another port of the multi-port memory device.
The new system has the processing power to perform the advanced signal processing necessary to compensate for one or more of the factors which lead to the overall poor performance of a conventional ASR-9 operating in an urban environment.
Because the new radar processing system is based on a conventional ASR-9, the cost of the new system is significantly lower than the cost would be if the performance concerns of the ASR-9 were addressed by designing and developing a replacement system from scratch.
The new surveillance radar processing system can be put on a single board or card which replaces an existing board of the conventional ASR-9, specifically, a Dual-Port Random Access Memory (DPRAM) board.
The single board with the new radar processing system replaces a DPRAM board with no further modifications to the conventional ASR-9 system.
In general, in one aspect, the invention features a radar processor which comprises a multi-port memory device having memory which can be accessed by at least three ports.
A first port receives input data from a data providing means.
A second port couples a first processor which performs radar processing



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