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Self-calibrating time interval meter
| Details |
Inventors: Knierim, Daniel G.; Jalovec, Lee J.;
Assignee: Tektronix, Inc. (Beaverton, OR)
Primary Examiner: Lall; Parshotam S.
Assistant Examiner:
Attorney, Agent or Firm: Jones; Allston L., Bedell; Daniel J.
A self-calibrating time interval meter including means for measuring time intervals using a dual-speed ramp technique. The time interval meter operates in a measurement mode to measure time intervals and operates in a calibration mode for calibration adjustments. In measurement mode, the time interval meter utilizes a dual-speed ramp technique to expand the time interval to be measured. A capacitor is rapidly charged by a first constant current source during the time interval to be measured, and is then slowly discharged by a second constant current source. The time required to discharge the capacitor is measured and utilized to compute a measurement of the time interval. In calibration mode, a flip-flop is alternately switched into and out of the circuit to provide two time interval measurements that differ by exactly one clock period of a known clock signal. A microprocessor subtracts the two measurements and compares the difference to the known clock period to determine a calibration error. The microprocessor, through a digital-to-analog converter, varies the current flow of the first constant current source to minimize the calibration error by compensating for drift in the current sources. |
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DETAILED DESCRIPTION What is claimed is: 1. A circuit for calibrating a time interval meter by establishing a known time interval, where said time interval meter is operable for measuring time intervals between the receipt of a start signal and the receipt of a stop signal, said circuit comprising: a clock signal generator having a constant and known frequency, said clock signal periodically alternates between a logic high state and a logic low state; sequential latch means coupled to receive said clock signal, said start signal, and a select signal for outputting said stop signal after an elapsed time interval has passed subsequent to the receipt of said start signal, wherein said select signal selects between a first elapsed time interval and a second elapsed time interval where said second elapsed time interval is one clock period longer than said first elapsed time interval, and wherein said known time interval is equal to the time difference between said first and second elapsed time intervals. 2. A circuit as in claim 1 wherein said sequential latch means comprises: first, second, and third flip-flops coupled to said clock signal and operable for respectively outputting first, second, and third output signals equal to the respective logic states of first, second, and third input signals when said flip-flops are clocked, said first flip-flop is clocked at a rising edge of said clock signal, said second and third flip-flops are clocked at a falling edge of said clock signal, said flip-flops are interconnected such that said first output signal is equal to said second input signal, and one of said first output signal and said second output signal is equal to said third input signal, wherein said first input signal is equal to said start signal and said third output signal is equal to said stop signal; and switching means coupled to said select signal for connecting one of said first output signal and said second output signal to said third flip-flop to form said third input signal, wherein said first elapsed time interval occurs when said first output signal is connected to said third input signal and said second elapsed time interval occurs when said second output signal is connected to said third input signal, and wherein said elapsed time interval is the time between a rising edge of said first input signal and a rising edge of said third output signal
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