Successive approximation analog-to-digital converter circuit

DETAILED DESCRIPTION OF THE INVENTION Now, embodiments of the present invention will be explained with reference to the accompanying drawings.
First, referring to FIG.
3, the successive approximation A/D converter circuit according to a first embodiment of the present invention will be explained.
FIG.
3 shows the successive approximation A/D converter circuit according to the first embodiment having a voltage comparing circuit 1 of the present invention and a circuit diagram of the input region.
In the first embodiment, the D/A conversion circuit 4 and the A/D conversion control circuit 5 are employed as is the same as in FIG.
2.
However, they are omitted for brevity.
In the first embodiment, an off set correction condenser C.
sub.
off is added in parallel to a sample-hold condenser C.
sub.
SH.
Different voltages are applied to the sampling period and the comparing period to correct the D/A conversion voltage V.
sub.
dac by .
DELTA.
V in such a way that the analogous input voltage V.
sub.
AIN is consistent with the D/A conversion voltage V.
sub.
DAC which corresponds to A/D conversion code of the theoretically obtained V.
sub.
AIN.
It is therefore possible to correct the offset error evenly (equally) contained in the overall D/A conversion voltages from MSB to LSB by relatively shifting by +.
DELTA.
V or -.
DELTA.
V.
In this way, the offset correction is attained.
Referring to FIG.
3, we will explain the offset correction of the successive approximation A/D converter circuit according to the first embodiment, more specifically.
In the sampling period, the switch SW.
sub.
SH is connected to a side of an analogous input voltage V.
sub.
AIN.
Simultaneously, the switch SW.
sub.
off is connected to a terminal voltage V.
sub.
off1 at a lower voltage side of the resistor circuit constituting the D/A conversion circuit.
As described in FIG.
2, in the sampling period, the switches SW.
sub.
AZN, SW.
sub.
AZP, SW.
sub.
0 are turned on.
As a result, a (-) input terminal and (+) output terminal, (+) input terminal and (-) output terminal, and (+) output terminal and (-) output terminal are individually connected to form a bypass circuit in the voltage comparing circuit 1