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 Apparatus and method for testing a memory array

Details
Inventors: Seymour, Edward Michael;
Assignee: International Business Machines Corp. (Armonk, NY)
Primary Examiner: Nguyen; Hoa T.
Assistant Examiner:
Attorney, Agent or Firm: Kordzik; Kelly K. Winstead Sechrest & Minick P.C., Davis, Jr.; Michael A.

There is disclosed a central controller for simultaneously testing the embedded arrays in a processor. Test data vectors are serially shifted into a latch and stored into each location in the embedded arrays of the processor. The test data are then read out of the embedded arrays into a read latch and serially shifted into a multiple input shift register, where a polynomial division is performed on the test vector data. If all memory locations in the embedded array function properly, a remainder value will result that is equal to a unique signature remainder for the test vectors used.

DETAILED DESCRIPTION The limitations inherent in the prior art are overcome by the present invention which provides a central ABIST controller which controls a plurality of ABIST test circuits through a serial communications link.
The present invention also simplifies the prior art ABIST test circuits by replacing large test vector data buffers and output comparator circuitry with serial input scan-in/scan-out registers.
In one embodiment of the present invention, there is provided an apparatus for testing an embedded memory array comprising: 1) a test data input latch for receiving a test data vector on a serial input of the test data input latch and writing the test data vector into a first location in the memory array, 2) an address buffer for receiving a test address vector on a serial input of the address buffer and applying the test address vector to the memory array, and 3) an output latch for reading the test data vector from the first location in the memory array.
Control logic is provided for scanning the test data vector and the test address vector into the test data input latch and the address buffer, respectively.
The control logic also generates a write signal that causes the test data vector to be written from the test data input latch into the first location in the memory array and generates a read signal that causes the test data vector to be read from the first location in the memory array into the output latch.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood.
Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention



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