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Phase lock-loop modulator using an arithmetic synthesizer
| Details |
Inventors: Nossen, Edward Joachim;
Assignee: RCA Corporation (New York, NY)
Primary Examiner: Kominski; John
Assistant Examiner:
Attorney, Agent or Firm: Wright; Carl M., Christoffersen; H., Cohen; Samuel
A phase lock loop has a phase modulator within the loop to produce an output signal of frequency shifted or modulated RF. The modulator is controlled by input signals via an arithmetic synthesizer. |
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DETAILED DESCRIPTION OF THE INVENTION FIG. 1 shows a voltage controlled oscillator (VCO) 14 coupled to a four-phase modulator 15 which is coupled to a programmable divide-by-N counter 17. The purpose of the counter 17 will be described below. The output signal from the counter 17 is coupled as one input signal to a phase detector 21, whose other input signal is from a clock source oscillator 11 which may be coupled thereto via a divide-by-R counter 12. The output signal from the phase detector 21 is filtered by a low pass filter 18 and coupled to control the frequency of the VCO 14. The bandwidth of this loop must be wide enough to include all the modulation frequencies of interest. Four-phase modulators and single side band modulators are well known in the art and need not be described in detail. (See, for example, U. S. Pat. No. 3,838,350 and, for phase modulators generally, U. S. Pat. No. 3,755,739. See also, Information Transmission, Modulation and Noise, Schwartz, 2d edition, (McGraw-Hill, 1970, Chap. 4). The four-phase modulator 15 is controlled by the output signal from an accumulator 16. The accumulator 16 and a frequency register 20 form an arithmetic synthesizer. The arithmetic synthesizer driving the four-phase modulator 15 makes possible the transmission of analog signals or digital signals, the analog signals being converted to digital signals by an analog-to-digital converter 19. The operation of an arithmetic synthesizer is described in detail in a patent to Butler (U. S. Pat. No. 3,689,914), assigned to the same assignee as this application. A digital accumulator is an operating device for adding an input digital signal to a stored digital signal in response to a control or clocking pulse. The output signal from the accumulator is the stored digital value, which is increased at each clocking pulse by an amount equal to the input signal. An accumulator can be assembled from commercially available devices. For example, an arithmetic-logic unit (ALU) such as an integrated circuit type SN 74181 (Texas Instruments, Inc
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