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Details
Inventors: Kelly, Michael G.; Emad, Pirooz;
Assignee: Hewlett-Packard Company (Palo Alto, CA)
Primary Examiner: Saadat; Mahshid D.
Assistant Examiner: Clark; S. V.
Attorney, Agent or Firm: Short; Brian R.

A ball grid array to integrated circuit interconnection. The interconnection includes a ball grid array substrate having a first surface and a second surface. The first surface comprising a plurality of substrate interconnection conductive pads. A power supply via connects a power supply conductive pad of the first surface to a first conductive area on the second surface. A ground via connects a ground conductive pad of the first surface to a second conductive area on the second surface. A decoupling capacitor connected between the first conductive area and the second conductive area. The interconnection further comprises an integrated circuit comprising a plurality of integrated circuit conductive pads. A plurality of smaller solder balls interconnect at least one of the integrated circuit conductive pads to at least one of the substrate interconnection conductive pads. A circuit board substrate is electrically interconnected by larger solder balls to the ball grid array substrate.

DETAILED DESCRIPTION The present invention includes an integrated circuit package which helps minimizes the EMI associated with the integrated circuit.
The integrated circuit package minimizes the length of power supply interconnections and provides power supply decoupling capacitors in close proximity to the power supply interconnections.
A first embodiment of the invention includes a ball grid array interconnection.
The interconnection includes a ball grid array substrate having a first surface and a second surface.
The first surface comprising a plurality of substrate interconnection conductive pads.
A power supply via connects a power supply conductive pad of the first surface to a first conductive area on the second surface.
A ground via connects a ground conductive pad of the first surface to a second conductive area on the second surface.
A decoupling capacitor connected between the first conductive area and the second conductive area.
The interconnection further comprises an integrated circuit comprising a plurality of integrated circuit conductive pads.
A plurality of smaller solder balls interconnect at least one of the integrated circuit conductive pads to at least one of the substrate interconnection conductive pads.
A circuit board substrate is electrically interconnected by larger solder balls to the ball grid array substrate.
A second embodiment is similar to the first embodiment.
The second embodiment includes the solder bumps forming the electrical interconnection between the circuit board substrate and the ball grid array substrate being attached to the first surface of the ball grid array substrate.
A third embodiment is similar to the first embodiment.
The third embodiment includes the solder bumps forming the electrical interconnection between the circuit board substrate and the ball grid array substrate being attached to the second surface of the ball grid array substrate.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention



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