CMOS output circuit with enhanced ESD protection using drain side implantation

DETAILED DESCRIPTION A principal object of the present invention is to provide an effective and very manufacturable output circuit that protects a CMOS integrated circuit from electrostatic discharge (ESD) events.
A further object of the present invention is to provide an output circuit that can withstand larger dc voltages on the output pin by cascading NMOS transistors.
A still further object of the present invention is to provide an output circuit with cascaded NMOS transistors and with enhanced ESD performance through the use of a p-implanted region under the drain.
Another object of the present invention is to provide an effective and very manufacturable method to fabricate a cascaded NMOS transistor output circuit with enhanced ESD performance in a CMOS integrated circuit device.
In accordance with the objects of this invention, a new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved.
A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad.
A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad.
A driver NMOS cascaded stack comprises first and second NMOS transistors.
The first NMOS transistor has the source connected to ground and the gate connected to the input signal.
The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad.
A p- implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.
A dummy NMOS cascaded stack comprises third and fourth NMOS transistors.
The third NMOS transistor has the gate and the source connected to ground.
The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad.
A p- implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source