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DMOS power transistors with reduced number of contacts using integrated body-source connections
| Details |
Inventors: Bulucea, Constantin; Rossen, Rebecca;
Assignee: Siliconix Incorporated (Santa Clara, CA)
Primary Examiner: Ngo; Ngan V.
Assistant Examiner:
Attorney, Agent or Firm: Skjerven, Morrill, MacPherson, Franklin & Friel, Kwok; Edward C.
Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well. |
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DETAILED DESCRIPTION In accordance with the present invention, two topologically different microcells are provided.
Each of these microcells is designed to reduce the total number of contacts per device in mid- to high-voltage DMOS transistors.
These cells or microcells use integrated connections between the source region and the body region, so as to be less sensitive to contact obturations such as those caused by particle contamination.
Each of these cells comprises either an elongated hexagonal cell or a buried deep-body cell.
Both cells are most efficiently used in high-current trench DMOS transistors, where the density of body contacts becomes prohibitive.
The cells may, however, be implemented in planar DMOS transistors as well.
The invention will be more readily understood by reference to the drawings and the detailed description.
As will be appreciated by one skilled in the art, the invention is applicable to power switching transistors in general, and is not limited to the specific embodiments disclosed.
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