Drain source protected MNOS transistor and method of manufacture

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A partial sectional view of a conventional drain source protected MNOS transistor is shown in FIG.
1 of the drawings.
It comprises an N type silicon mesa 4 deposited in a sapphire substrate (not shown).
Drain region 6 and source region 5 are established by P+ implantation.
The mesa is covered with a layer 7 of silicon dioxide and a layer 8 of silicon nitride.
The structure also includes gate electrode 9 and source and drain electrode (not shown).
In the standard drain source protect MNOS memory transistor shown in FIG.
1 the deposited nitride layer 8 overlaps the thick oxide protected non-memory regions.
The thickness of the nitride layer 8 and the charge at the nitride thick oxide interface both affect the threshold of this non-memory region.
Since the operating characteristics of the drain source protected memory transistor depend on both the memory and non-memory characteristics, it is desirable to have independent control of their processing parameters.
This is accomplished by a method of creating a drain source protected memory structure where the memory nitride is present only in the memory section of the device.
In addition, the process is self-aligning such that the thermal gate oxide is grown in all regions other than the memory section.
The process of the invention is hereinafter described having reference to FIGS.
2-9.
Having reference now to FIG.
2, a silicon mesa 11 is fabricated on a substrate member 10.
Substrate member 10 is of electrically insulating material such as sapphire.
A source region 12 and a drain region 13 are established by P+ implantation and a 20-30 A layer 15 of tunneling or memory oxide is grown over the mesa.
A 300 A layer 14 of memory silicon nitride is then deposited over the tunneling oxide layer.
A 2000 - 3000 A masking silox layer 16 is then deposited and etched to leave silox in the memory regions as shown in FIG.
3.
The silicon nitride and tunneling oxide layers are then chemically etched and the silox is stripped to leave the isolated memory regions shown in FIG