EEPROM cell with integral select transistor

DETAILED DESCRIPTION An electrically programmable and electrically erasable memory cell formed in a silicon body is described.
The cell includes a first and second spaced-apart regions of a first conductivity type which define a channel.
A first gate member (floating gate) which is completely surrounded with insulation, extends from at least the edge of the first of the regions to over the channel.
A second gate member (control gate) includes a portion which extends over the first gate member, the second gate generally extends from at least the edge of the first region, over the channel, and to at least the edge of the second region.
A third region of a second conductivity type is formed in the body.
This third region is contiguous with the edge of the second region and extends to at least the edge of the first gate member.
The cell thus includes both a memory device and an integrally formed select device.