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ESD protection circuit
| Details |
Inventors: Li, Sheau-Suey; Ong, Randy T.; Broydo, Samuel; Duong, Khue;
Assignee: Xilinx, Inc. (San Jose, CA)
Primary Examiner: Carroll; J.
Assistant Examiner:
Attorney, Agent or Firm: Edel M. Young, Xilinx, Inc., Murabito, Esq.; Anthony C. Wagner, Murabito & Hao
An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage. |
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DETAILED DESCRIPTION According to the present invention, ESD protection is increased by providing one of the following structures.
First, the P-channel pull-up output transistor can be replaced by an N-channel transistor plus an inverter (so the output signal is inverted before driving the N-channel pull-up transistor).
This has the advantage of providing the parasitic bipolar transistor during an ESD event in which VCC is high and the pad is low.
But it has the disadvantage during normal operation of not pulling the pad output voltage all the way to the positive rail.
As a second alternative, the P-channel pull-up output transistor is retained but protected by a split bipolar transistor having its collector connected to the positive rail, its base connected to the negative rail, and its emitter connected to the pad.
An ESD event in which the positive rail experiences a positive voltage, the pad experiences a negative voltage and the negative rail is left floating (near zero volts) will turn on this split bipolar transistor and protect the P-channel output driver.
As a third alternative, the P-channel pull-up transistor can be retained to provide the rail-to-rail output voltage swing during operation and an N-channel transistor may be provided in parallel with the P-channel transistor to provide the parasitic path during an ESD event.
Also, according to the present invention, components are sized, shaped, and positioned to achieve improved ESD protection.
In particular, base-to-emitter resistors in the ESD protection devices are sized and shaped to have higher resistance than base-to-emitter resistance of the parasitic bipolar transistors which exist in parallel with output driver pull-down N-channel MOS transistors.
This sizing and shaping prevents the output drivers from going into snap-back mode before the ESD protection device goes into snap-back mode, and thus protects the output drivers from excessive current.
As another feature of the invention, a plurality of ESD protection circuits is combined
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