Electrostatic protection structure for MOS circuits

DETAILED DESCRIPTION The present invention is directed to an ESD protection circuit which includes a pair of lateral NPN transistors each having an emitter, collector and base.
The transistors are connected in series with the emitter of one transistor being connected to the collector of the other transistor.
A terminal is connected to the collector of one transistor and a terminal is connected to the emitter of the other transistor.
The bases of the two transistors are connected together and are floating.
Another aspect of the present invention is a semiconductor device forming an ESD protection circuit.
The semiconductor device includes a substrate of single crystalline silicon having a surface.
A layer of an insulating material is on the surface of the substrate and a thin layer of single crystalline silicon is on the insulating layer.
A pair of NPN lateral transistors are in the silicon layer with each transistor having a spaced pair of N+ type conductivity regions with a P- type conductivity region between and contacting the N+ type regions.
One of the N+ type regions of one of the transistors is electrically connected to one of the N+ type regions of the other transistor, and means are provided which electrically connects the P-type regions together.