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Home Semiconductor manufacture High-speed-on-chip-windowed-centroiding-using-photodiode-based-CMOS-imager

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 High-speed on-chip windowed centroiding using photodiode-based CMOS imager

Details
Inventors: Pain, Bedabrata; Sun, Chao; Yang, Guang; Cunningham, Thomas J.; Hancock, Bruce;
Assignee: California Institute of Technology (Pasadena, CA)
Primary Examiner: Couso; Jose L.
Assistant Examiner: Patel; Kanji
Attorney, Agent or Firm: Fish & Richardson P.C.

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

DETAILED DESCRIPTION The present disclosure describes an on-focal plane centroid computation circuit that is compatible and integrated with CMOS imagers implemented in conventional or modified CMOS technology.
In the present disclosure, a photodiode-based CMOS active pixel sensor (APS) is described as an example of a CMOS imager that may be used.
Overview The centroid computation circuit design allows accurate X- and Y-centroid computation from a user-selectable window of interest.
The circuit also allows window location and size to be programmable.
The circuit may be designed to dissipate less power than the prior art designs, which may enable a real-time, miniature tracking system.
In one implementation, the centroid computation circuit utilizes a switched capacitor network having only passive elements such as capacitors and switches.
The circuit further allows column-parallel computation that enables X- and Y-centroid computations to be performed substantially simultaneously.
This provides low power consumption and high accuracy computation to better than 0.
05 pixel accuracy.
The accuracy may be achieved under most lighting conditions, while maintaining high update rates (20-50 KHz) that make the chip attractive for use in real-time image-based control systems.
The photodiode-based CMOS imager design provides improved steady state and dynamic response.
In this design, both the pixel sensor and the clocking scheme are modified to allow imager operation with reset level independent of signal strength under steady state or dynamic conditions.
The pixel is reset in "soft-reset" allowing low-reset noise and high power supply rejection ratio ("PSRR").
However, its steady state and dynamic response may be made to follow that obtained with "hard-reset".
Hence, the design provides substantially reduced image lag and high linearity even under low-light levels compared to conventional imager designs.
The image lag was measured to be less than 1% compared to 10% in conventional imagers with soft-reset



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