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Integrable MOS and IGBT devices having trench gate structure
| Details |
Inventors: Gilbert, Percy V.; Neudeck, Gerold W.;
Assignee: Purdue Research Foundation (West Lafayette, IN)
Primary Examiner: Wojciechowicz; Edward
Assistant Examiner:
Attorney, Agent or Firm: Townsend and Townsend Khourie and Crew
A power semiconductor device which is integrable in an integrated circuit includes a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween, second and third doped regions of a second conductivity type formed in the first doped region, the second and third doped regions being spaced apart and abutting the first surface, and fourth and fifth doped regions of the first conductivity type respectively formed in the second and third doped regions and abutting the first surface. Sixth and seventh doped regions extend from the first surface into the first region, the sixth region being adjacent to the second and fourth regions and spaced therefrom by an electrically insulative layer, the seventh region being adjacent to the third and fifth regions and spaced therefrom by an insulative layer. The first doped region extends toward the first surface between the sixth and seventh regions and separated therefrom by an electrically insulative layer of variable thickness suitable for voltage blocking. An eighth doped region in the first doped region between the sixth and seventh regions abuts the first surface and forms the drain of a MOSFET or the anode of an IGBT. In fabricating the device, reactive ion etching is used to from a trench in which the sixth and seventh regions are formed. The trench is filled by epitaxially grown semiconductor material in which the eighth doped region is formed. The fourth and fifth doped regions form the source of a MOSFET or a cathode of an IGBT. All ohmic contacts to the device can be made on the first surface. |
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DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS FIG.
3 is a section view of a power MOSFET device in accordance with one embodiment of the invention, and FIG.
4 is a section view of an IGBT device in accordance with one embodiment of the invention.
The two devices are similar in structure and like elements have the same reference numeral.
Referring to FIG.
3, the device is fabricated in an N.
sup.
- doped silicon substrate 30.
The source and channel regions of the device are formed by double diffused regions including N.
sup.
+ surface region 32 formed in a P doped region 34, and N.
sup.
+ region 36 formed in a P region 38.
Two doped polysilicon gates 40, 42 extend vertically from the surface of the semiconductor wafer into the N.
sup.
- region 30.
Gate electrode 40 is adjacent to N.
sup.
+ region 32 and P region 34 and separated therefrom by silicon oxide insulation 44 (gate oxide), and gate electrode 42 is adjacent to the N.
sup.
+ region 36 and P region 38 and separated therefrom by silicon oxide 46 (gate oxide).
The N.
sup.
- region 30 extends towards the surface between the gate electrodes 40, 42 and is insulated therefrom by the variable thickness silicon oxide 44, 46 (blocking voltage oxide) which respectively envelope the gate electrodes 40, 42.
In the power MOSFET device, an N.
sup.
+ surface region 48 is formed in the N.
sup.
- region 30 between the gate electrodes and functions as the drain of the MOSFET.
A drain contact 50 is made thereto.
N.
sup.
+ regions 32, 36 function as the source regions of the device, and contacts 52 and 54 on the surface of the device contact the N.
sup.
+ regions 32, 36 as well as the P doped regions 34, 38.
The P doped regions can have more heavily doped P.
sup.
+ regions to facilitate ohmic contact thereto, as will be described hereinbelow with reference to FIGS.
5A-5F.
Thus, the device has the advantages of all contacts formed on one surface of the device, yet current flow is in a vertical direction.
As noted above, the section view of the IGBT of FIG.
4 is similar to the MOSFET device of FIG
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