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Integral honeycomb-like support of very thin single crystal slices
| Details |
Inventors: Kendall, Don Leslie; Knowles, Jr., John C.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Rutledge; L. Dewayne
Assistant Examiner: Davis; J. M.
Attorney, Agent or Firm: Levine; Harold, Comfort; James T., Honeycutt; Gary C.
The disclosure relates to the formation of very thin silicon slices, 1/10 of a mil, and the mechanical strengthening of such thin silicon slices and to the formation of electronic circuitry in such slices and the use thereof. These slices are formed, in accordance with one embodiment of the invention, by etching grooves in an n+ wafer using an orientation dependent etch and etching along the {111} plane in {110} n+ wafers. After oxide removal, the surface of the wafer opposite the grooves is epitaxially coated with n-type silicon and the original grooves are then further etched by an electrolytic etch or by a concentration dependent etch which will remove only the n+ material, thereby leaving the thin wafer with a honeycomb-like supporting structure with struts in the shapes of parallelograms, diamonds and the like. The thin slice can be used to purify electron beams since, for given energies, only ions passing in the direction of the lattice structure or along the channel will completely pass through the slice, the other ions being stopped by collisions with the atoms of the silicon slice. The slice can also be used as a channel multiplier since light impinging on the slice will generate electrons which will pass between struts or honeycomb-like members and gradually pick up additional electrons by secondary emission. These electrons are made to fall on a phosphor screen or the like whereby light is again generated, but in multiplied fashion. |
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DETAILED DESCRIPTION What is claimed is: 1.
A method of forming very thin semiconductor slices which comprises the steps of: a.
providing a wafer of semiconductor material of predetermined crystallographic orientation and of predetermined conductivity type; b.
forming a mask on a surface of said wafer; c.
etching in said wafer through said mask to form parallelogram shaped grooves d.
removing said mask and depositing semiconductor material in said grooves and along said surface of said wafer of the same conductivity type as said wafer but of lower dopant concentration; and e.
removing the original wafer.
2.
A method as set forth in claim 1, wherein said etch in step (c) is an orientation dependent etch.
3.
A method as set forth in claim 1, wherein step (e) includes etching using an electrolytic etch.
4.
A method as set forth in claim 2, wherein step (e) includes etching using an electrolytic etch.
5.
A method as set forth in claim 1, wherein step (e) includes etching with a concentration dependent etch.
6.
A method as set forth in claim 2, wherein step (e) includes etching with a concentration dependent etch.
7.
A method as set forth in claim 1, wherein said grooves are formed in the shape of parallel struts.
8.
A method as set forth in claim 6, wherein said grooves are formed in the shape of parallel struts.
9.
A method as set forth in claim 1, wherein said grooves are formed in the shape of a parallelogram array.
10.
A method as set forth in claim 6, wherein said grooves are formed in the shape of a parallelogram array.
11.
A method of forming very thin semiconductor slices which comprises the steps of: a.
providing a wafer of semiconductor material of predetermined conductivity type with more concentrated layer of said conductivity type at one surface; b.
forming a mask over said layer; c.
depositing said semiconductor material through said mask onto said layer to form an elevated pattern of said semiconductor material of said more concentrated conductivity type in the shape of the pattern of said mask; d
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