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Thermal CVD process for depositing a low dielectric constant carbon-doped silicon oxide film |
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Semiconductor power conversion apparatus |
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Silicon metallographic etch |
| OF THE INVENTION Referring to FIG. 1 there is shown a graph showing the change in etch rate at two ... |
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Semiconductor device including plateless package fabrication method |
| The foregoing and other objects and advantages are achieved in the present invention through the ... |
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Stress insensitive integrated circuit |
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Hall-type transducing device |
| In designing a Hall-type transducer to operate in conjunction with a comparatively small, ferrite-... |
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Topography for integrated circuit operational amplifier having low impedance input for current feedback |
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Operational amplifier with stabilized DC operations |
| Embodiment 1 FIG. 1 shows a first embodiment of a CMOS operational amplifier according to our ... |
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Low power digital CMOS compatible bandgap reference |
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Method for fabrication and structure for high aspect ratio vias
| Details |
Inventors: Zhao, Bin;
Assignee: Conexant Systems, Inc. (Newport Beach, CA)
Primary Examiner: Nelms; David
Assistant Examiner: Nhu; David
Attorney, Agent or Firm: Farjami & Farjami LLP
A via is first etched in a dielectric. Then a conformal layer is deposited over the dielectric and the via to reduce an initial width of the via to a target width. A trench is then etched in the dielectric and the conformal layer. Since the width of the via is reduced from the initial width to the target width, the resulting final via has a high aspect ratio. The via and the trench are then filled with metal which contacts an interconnect metal situated below the via. In one embodiment, copper is used to fill the via and the trench and also as the interconnect metal below the via. In one embodiment, the dielectric is silicon dioxide or fluorinated silicon dioxide and the conformal layer is silicon dioxide. In another embodiment, the dielectric is silicon dioxide or fluorinated silicon dioxide while the conformal layer is silicon nitride. To etch the trench in the dielectric and the conformal layer, a timed exposure to a carbon fluoride based plasma is employed. Alternatively, instead of timing the exposure to plasma, a suitable etch stop layer is used. In the embodiment where a conformal layer of high dielectric constant is used, the conformal layer remaining on the dielectric surface is removed using either chemical mechanical polishing or by plasma etching. The final structure is a via and a trench where the via's side walls are covered by the conformal layer while the trench's side walls are not covered by the conformal layer. |
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DETAILED DESCRIPTION The present invention discloses method for fabrication and structure for high aspect ratio vias. According to the invention's method, a via is first etched in a dielectric. Then a conformal layer is deposited over the dielectric and the via. The conformal layer reduces an initial width of the via to a target width. A trench is then etched in the dielectric and the conformal layer. Since the width of the via is reduced from the initial width to the target width, the resulting final via has a high aspect ratio, while the fabrication of the final high aspect ratio via has been made much easier as compared to the conventional fabrication methods. The via and the trench are then filled with metal which contacts an interconnect metal situated below the via. In one embodiment of the invention copper is used to fill the via and the trench and also as the interconnect metal below the via. In one embodiment of the invention, the dielectric is silicon dioxide or fluorinated silicon dioxide and the conformal layer is silicon dioxide. In another embodiment of the invention, the dielectric is silicon dioxide or fluorinated silicon dioxide while the conformal layer is silicon nitride. In order to etch the trench in the dielectric and the conformal layer, a timed exposure to a carbon fluoride based plasma is employed. Alternatively, instead of timing the exposure to plasma, a suitable etch stop layer is used. In the embodiment of the invention where silicon nitride is used as the conformal layer, the silicon nitride remaining on the dielectric is removed using either chemical mechanical polishing or a carbon fluoride based plasma. The invention's final structure is a via and a trench where the via's side walls are covered by the conformal layer while the trench's side walls are not covered by the conformal layer.
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