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Method for forming a MOSFET with substrate source contact
| Details |
Inventors: Johnsen, Robert J.; Sanders, Paul W.;
Assignee: Motorola Inc. (Schaumburg, IL)
Primary Examiner: Hearn; Brian E.
Assistant Examiner: Fleck; Linda J.
Attorney, Agent or Firm: Handy; Robert M., Barbee; Joe E.
A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-,P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications. |
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DETAILED DESCRIPTION Accordingly, it is an object of the present invention to provide an improved means and method for MOSFETS having a back-side source contact.
It is a further object to provide an improved means and method for MOSFETS which can be mounted in a grounded-source package without need for an insulator between the MOSFET die and the package flange.
It is a still further object to provide an improved means and method for MOSFETS without need for source contact wirebonds.
These improvements are especially intended for high frequency and/or high power MOSFETS although they are also useful at lower frequencies as well.
The foregoing and other objects and advantages are provided by a vertical MOSFET device comprising a semiconductor substrate having first and second opposed surfaces, a drain region adjacent the first surface, a channel forming (body) region underlying the drain region, a source region underlying the channel forming region and a gate dielectric and electrode on a portion of the channel forming region between the source and drain regions for modulating the conductivity therebetween, and a buried ohmic contact shorting part of the channel forming region to the underlying source region.
The source region extends to or is contacted from the second surface.
The buried ohmic contact is desirably formed at the bottom of a first cavity extending from the first surface into the substrate to the source region and covered with a semi-insulator or dielectric.
This first cavity desirably has a first sidewall portion adjacent the first surface which is substantially vertical and a second sidewall portion below the first sidewall portion which is inclined at an angle to that the PN junction between the channel forming region and the source region intersects the angled sidewall portion of the cavity.
The PN junction is covered with a buried conductor which makes ohmic contact to the semiconductor on both sides of the PN junction, thereby locally shorting the two regions together
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