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Mask surrogate semiconductor process employing dopant-opaque region |
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High speed, low gate/drain capacitance DMOS device |
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Method for the preparation of a pattern overlay accuracy-measuring mark |
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Power insulated-gate transistor having three terminals and a manufacturing method thereof |
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High-voltage transistor and manufacturing method therefor |
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Inelastic, heat-elasticizable sheet material for diapers |
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Disposable diaper with a repositionable tape tab fastener |
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Cryoenucleation tool |
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Method of applying a male incontinence device |
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Method for forming shallow source/drain extension for MOS transistor
| Details |
Inventors: Yu, Bin;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Mintel; William
Assistant Examiner:
Attorney, Agent or Firm: LaRiviere, Grubman & Payne, LLP
A method for making a ULSI MOSFET chip includes forming the gate of a transistor on a silicon substrate, covering the gate with a SiON protective layer, and then implanting a pre-amorphization high dose Si or Ge implant into the substrate. Next, dopant is pre-implanted into the substrate to promote subsequent formation of source and drain extensions, with the SiON layer protecting the gate from the pre-amorphization high dose Si or Ge and from the dopant. Undoped polysilicon and polygermanium is then deposited onto the substrate adjacent the gate at relatively low temperatures (600.degree. C.) to establish elevated source and drain regions without excessively thermally stressing the chip. The SiON layer is removed from the gate, and the gate and elevated source and drain regions are implanted with dopant, followed by rapid thermal annealing to form the source and drain extensions in the substrate below the gate. The gate and elevated source and drain regions are then silicidized. |
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DETAILED DESCRIPTION OF THE INVENTION". BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of a semiconductor device made according to the present invention, shown in combination with a digital processing apparatus; FIG. 2 is a flow chart showing the steps of the present invention; FIG. 3 is a side view of the device after the gate polysilicon and gate oxide has been formed, during preamorphization implanting; FIG. 4 is a side view of the device after the nitride spacers have been formed, during source and drain extension region dopant implantation; FIG. 5 is a side view of the device after deposition of the undoped polysilicon adjacent the gate; FIG. 6 is a side view of the device after the protective SiON layer has been removed, the source and drain regions have been implanted with dopant, and the device has undergone rapid thermal annealing to form the source and drain extension regions; and FIG. 7 is a side view of the device after silicidation. DETAILED DESCRIPTION OF THE INVENTION Referring initially to FIG. 1, a semiconductor device embodied as a chip 10 is shown incorporated into a digital processing apparatus such as a computer 12. The chip 10 is made in accordance with the below disclosure. Now referring to FIGS. 2 and 3, as indicated at block 14 in FIG. 2 and as shown in FIG. 3, using conventional semiconductor fabrication techniques including low pressure chemical vapor deposition (LPCVD) and appropriate etching and lithography, a transistor gate, generally designated 16, is formed on a silicon or other semiconductor substrate 18. As shown, the gate 16 includes a thin insulating gate oxide layer 20 that faces the substrate 18 and a gate polysilicon stack 22 on the gate oxide layer 20. Additionally, as indicated at block 24 in FIG. 2 and as shown in FIG. 3, a protective silicon-oxygen-nitrogen (SiON) layer 26 is deposited on the top of the gate 16. Then, an amorphization substance such as high-dose silicon (Si) or germanium (Ge), represented by the dashed line 28, is implanted into the substrate 18 as indicated by the arrows 30
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***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST*** *** NO IMAGES AVAILABLE***
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