Method of forming a flash EEPROM device by employing polysilicon sidewall spacer as an erase gate

DETAILED DESCRIPTION What is claimed is: 1.
A method of fabricating a Flash EEPROM device having an array of cells, the method comprising: 1) providing peripheral PMOS and NMOS transistors and a flash EEPROM device on a silicon substrate, wherein said providing a flash EEPROM device comprises: providing a partially processed semiconductor wafer including a floating gate oxide on a substrate, a first polysilicon layer disposed on the floating gate oxide, a second polysilicon layer disposed thereon with an interpolysilicon dielectric layer therebetween, and an oxide cap on top of the second polysilicon layer; 2) patterning and etching the oxide cap and the second polysilicon layer so that a portion of the second polysilicon layer form a control gate structure presenting sidewalls; 3) forming dielectric spacers on the sidewalls of the control gate structure, on peripheral PMOS and NMOS transistors, the dielectric spacers having a thickness ranging between 350 .
ANG.
and 650 .
ANG.
; 4) etching the first polysilicon layer so that a portion of the first polysilicon layer form a floating gate structure, using the oxide cap and the dielectric spacers as hard masks for the etching; 5) implanting Boron to a sufficient concentration to shift an erase gate threshold voltage to around 1V; 6) stripping a portion of the floating gate oxide on the silicon substrate; 7) growing an erase gate oxide with thickness between 50 .
ANG.
and 250 .
ANG.
; 8) growing a poly tunnel oxide on sidewalls of the floating gate structure during step (7); 9) depositing and etching back an erase-gate polysilicon layer to form polysilicon sidewall spacers on said flash EEPROM device, said peripheral PMOS and NMOS transistors, wherein said polysilicon sidewall spacers having a thickness between 0.
1 um and 0.
3 um; 10) forming polysilicon contact pads with a photolithography mask during step (9); 11) stripping selected portions of the layer polysilicon sidewall spacers on one side of the flash EEPROM device, using a photolithography mask; 12) etching a field oxide along source lines; 13) implanting N