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 Method of making a magnetoelectronic device

Details
Inventors: Johnson, Mark B.;
Assignee:
Primary Examiner: Picardat; Kevin M.
Assistant Examiner:
Attorney, Agent or Firm: Law +

A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array. This latter arrangement also permits a bias supply to be applied to each cell in the array, increasing the output signal level, and the signal to noise ratio. A high resistance element such as a resistor or diode can also be used as the isolation element depending on the particular application. In a preferred embodiment, the hybrid memory device and associated selector are combined and integrally fabricated using conventional semiconductor processing techniques to increase the integration density of memory arrays using such devices

DETAILED DESCRIPTION An object of the present invention therefore is to provide an improved architecture for a hybrid Hall Effect device to be used as a memory cell in a memory array.
A further object of the present invention is to provide an improved architecture for a random access memory array of hybrid Hall Effect memory cells which permits a bias voltage (or current) to be provided to each such cell, thus resulting in improved signal level and signal-to-noise ratio characteristics for such array.
Another object of the present invention is to provide an improved memory cell for application in a memory array environment, which affords improved cell isolation and reduced cross talk between cells in the array.
According to the present invention, an array of modified Hall Effect plate memory elements with improved performance is formed by providing the bias source I.
sub.
B or (V.
sub.
B) directly to each cell in the array to increase the SNR.
The outputs of the Hall Effect plate memory elements can be coupled to a select transistor which acts as an isolation element to reduce cross-talk between cells in the array.
In this way, the magnetization state of the ferromagnetic layer and the output of the Hall Effect plate for each hybrid memory cell is retained and isolated from other hybrid memory cells.
The bias source and ground for the cells are provided by additional individual levels of lithography, and this choice increases the number of fabrication steps (and levels) by comparison with the simpler array described earlier.
However, the hybrid Hall Effect device requires far fewer levels than conventional dynamic random access memories (DRAM) and this economy of fabrication is only marginally diminished by the addition of a few levels.
In the preferred cell architecture, one selection transistor is fabricated within each cell.
When a select transistor for a particular cell is addressed the Hall voltage developed by that cell is the only voltage transmitted to the input line of a sense amplifier that is common to a column of cells



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