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Details
Inventors: Kimura, Daisuke;
Assignee: Sharp Kabushiki Kaisha (Osaka, JP)
Primary Examiner: Quach; T. N.
Assistant Examiner:
Attorney, Agent or Firm: Nixon & Vanderhye

A method of manufacturing a semiconductor device is disclosed which may form a very minute interconnection pattern having line width less than that of an interconnection pattern formed by a photolithography technique. In the method of manufacturing a semiconductor device, after patterning by a photolithography technique polysilicon layer 3a and nitride layer 4a laminated in order on semiconductor silicon substrate 1, an oxide film is formed in a self-alignment manner in the polysilicon layer by thermal oxidation treatment at a high temperature and a nitride film is removed by etching back the whole surface. The polysilicon layer is divided into two by carrying out etching with the oxide film used as mask. It is possible to form two interconnection patterns in the space for one interconnection pattern formed by a photolithography technique using such a manufacturing method.

DETAILED DESCRIPTION One object of the present invention is to form a very minute interconnection pattern having line width less than that of an interconnection pattern formed using a conventional photolithography technique in a method of manufacturing a semiconductor device.
Another object of the present invention is to form easily an interconnection pattern having line width less than that of an interconnection pattern formed using a conventional photolithography technique in a method of manufacturing a semiconductor device.
In brief, in one aspect of the present invention, a manufacturing method of a semiconductor device is a method of manufacturing a semiconductor device having an interconnection pattern formed on a semiconductor substrate using a photolithography method, including the steps of forming an interconnection material layer including silicon on a semiconductor substrate and an oxidation resistance layer thereon; patterning the interconnection material layer and the oxidation resistance layer by a photolithography method; forming by thermal oxidation treatment an oxide film on an area of the top surface of the patterned interconnection material layer, excluding the center portion along a predetermined direction of the same; removing the oxidation resistance layer by etching the whole surface; and forming a pair of first and second interconnection patterns by removing with the oxide film used as mask the center portion along a predetermined direction of the patterned interconnection material layer.
In operation, an oxide film is formed by thermal oxidation treatment on an area of the top surface of the patterned interconnection material layer, excluding the center portion along a predetermined direction of the same; the center portion along a predetermined direction of the patterned interconnection material layer is removed with the oxide film used as mask after removing an oxide resistance layer; and a pair of first and second interconnection patterns are formed.
As a result, a pair of interconnection patterns are provided using line width for one interconnection pattern formed by a conventional photolithography method



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