Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Semiconductor manufacture Method-of-producing-a-metal-oxide-semiconductor-device-with-raised-source-drain

 Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current
I claim: 1. A trench MOSFET comprising: (a) at least one pedestal, that functions as a vertically-...


 Insulated gate static induction transistor and integrated circuit including same
Therefore, an object of the present invention is to provide an insulated-gate static induction ...


 Mask surrogate semiconductor process employing dopant-opaque region
A general object of the present invention, therefore, is to provide a novel manufacturing procedure ...


 High speed, low gate/drain capacitance DMOS device
It is a purpose of the present invention to provide a new and improved method of producing high ...


 Method for the preparation of a pattern overlay accuracy-measuring mark
Therefore, it is an object of the present invention to overcome the above problems encountered in ...


 Power insulated-gate transistor having three terminals and a manufacturing method thereof
OF THE PREFERRED EMBODIMENTS FIGS. 2 illustrates the structure of an insulated-gate transistor in ...


 High-voltage transistor and manufacturing method therefor
Therefore, it is an object of the present invention to provide a high-voltage transistor which can ...


 Inelastic, heat-elasticizable sheet material for diapers
In FIG. 1, heat-shrinkable composite 10 comprises a plurality of parallel elastomeric strands, ...


 Disposable diaper with a repositionable tape tab fastener
According to the present invention, a disposable diaper is provided which has a pressure-sensitive ...


 Cryoenucleation tool
I claim: 1. Apparatus for cryoenucleating a tumor of the eye comprising: a spoon of thermally ...


 Method of producing a metal oxide semiconductor device with raised source/drain

Details
Inventors: Lin, Ming-Ren;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Niebling; John F.
Assistant Examiner: Hack; Jonathan
Attorney, Agent or Firm:

A semiconductor device and a method of making the device with a raised source/drain has a semiconductive material that is non-selectively deposited in a layer over the device area. The semiconductive material is then etched to form spacers that will form the raised soure/drain areas following doping of the spacers. The gate of the semiconductor device is protected during the etching by an etch stop layer that is grown or deposited over the structure to be protected, e.g., the gate, prior to the deposition of the semiconductive material layer. Lightly doped drain ion implantation is performed prior to the formation of the spacers, and source-drain ion implantation is performed preferably after the formation of the spacers, to create the shallow junctions.

DETAILED DESCRIPTION There is a need for a method of making a semiconductor device with raised source/drain structure, in a readily manufacturable process that is cost effective.
This and other needs are met by an embodiment of the present invention which provides a method of forming a semiconductor device with raised source and drain, comprising the steps of providing an etch stop layer on a gate of the semiconductor device, depositing a layer of semiconductor material over the semiconductor device, and etching the semiconductor layer to form spacers of a desired width and thickness.
The etch stop layer protects the gate during the etching.
The spacers are doped to create the raised source and drain.
In certain embodiments, the semiconductor layer is made of amorphous silicon or polysilicon.
In alternative embodiments, the gate material is different from the spacer material such that the etch stop layer is not necessary.
In these embodiments of the present invention, the two materials selected as the gate and the semiconductor material should have good selectivity.
Since the steps involved in forming the spacers comprise depositing of the semiconductor layer and etching, a simpler and more cost effective manner of forming the raised source/drain is provided, in comparison to the conventional selective epi deposition method.
Also, there is a lower thermal budget required for the method of the present invention than for the selective epi deposition method of the prior art.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of forming a semiconductor device with raised source and drain, comprising the steps of non-selectively depositing a layer of semiconductor material over the semiconductor device, etching the semiconductor layer to form spacers of a desired width and thickness, and doping the spacers to create the raised source and drain.
The earlier stated needs are also met by another embodiment which provides a semiconductor device having a raised source/drain, comprising a substrate with shallow junctions, a gate, and a raised source/drain formed of non-selectively deposited semiconductive material on the substrate



Related patents
  Method for forming shallow source/drain extension for MOS transistor
OF THE INVENTION". BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of a semiconductor device made according to the present invention, shown in combination ...
  Laser texturing
The present invention is directed to providing a contactless technique for imparting a texture to a surface by promoting a chemical etching reaction between a gaseous ...
  Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
FIG. 2 shows a trenched DMOS transistor structure in accordance with the present invention. The substrate (drain) region 10 is in the lower portion of the semiconductor ...
  Semiconductor device and power converter using same
The semiconductor device according to the present invention has a pair of main surfaces. On one main surface side, the surface of a first semiconductor region of a first ...
  Self-aligned channel stop for trench-isolated island
In accordance with the present invention, the need to provide a separation region between the trench and a device region within the island, which results in an unwanted ...
  DMOS power transistors with reduced number of contacts using integrated body-source connections
In accordance with the present invention, two topologically different microcells are provided. Each of these microcells is designed to reduce the total number of ...
  Trench depletion MOSFET
The present invention is a trench power MOSFET with a unique structure which overcomes the above-noted deficiencies of the prior art. Advantageously, the present ...
  ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST*** *** NO IMAGES AVAILABLE***
Description:...
  Method for forming a MOSFET with substrate source contact
Accordingly, it is an object of the present invention to provide an improved means and method for MOSFETS having a back-side source contact. It is a further object to ...
  Integrable MOS and IGBT devices having trench gate structure
OF ILLUSTRATIVE EMBODIMENTS FIG. 3 is a section view of a power MOSFET device in accordance with one embodiment of the invention, and FIG. 4 is a section view of an IGBT...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved