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Operational amplifier with stabilized DC operations
| Details |
Inventors: Chimura, Tsuyoshi; Higashi, Masahiko; Satoh, Tatsumi;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Callahan; Timothy P.
Assistant Examiner: Englund; Terry L.
Attorney, Agent or Firm: Kempler; William B., Donaldson; Richard L.
An operational amplifier with improved operational speed, as well as low power consumption, arranges a current mirror made of the pMOS transistors PT.sub.17 and PT.sub.18 in the stage after the initial-stage differential amplifier, supplies the output of the initial-stage differential amplifier to the gate of the nMOS transistor NT.sub.14, supplies the current flowing through the current mirror to the output stage side by a current mirror made of the pMOS transistors PT.sub.15 and PT.sub.16, and lastly a pMOS transistor PT.sub.19 is connected as a constant-current source between the supply line for the power supply voltage V.sub.DD and the node ND.sub.12, and makes the idling current I.sub.19 flow in the node ND.sub.12. Due to this, stabilization of DC operations during normal states and when shifting its states can be designed without considering the characteristics in the vicinity of the threshold voltage of pMOS transistor PT.sub.16, and thus stringent controls in the manufacturing process and the like are unnecessary. |
|
DETAILED DESCRIPTION Embodiment 1 FIG.
1 shows a first embodiment of a CMOS operational amplifier according to our invention, in which parts the same as those in FIG.
8 have the same reference numerals.
An input terminal T.
sub.
IN receives an input signal V.
sub.
IN and an output terminal T.
sub.
OUT provides an output signal V.
sub.
OUT to a capacitive external load C.
sub.
L.
PT.
sub.
11 -PT.
sub.
19 are pMOS transistors, NT.
sub.
11 -NT.
sub.
15 are nMOS transistors, I.
sub.
11 is a current source, and C.
sub.
11 is a phase compensating capacitor.
A high gain, initial-stage differential amplifier like that in FIG.
8 receives the input voltage V.
sub.
IN at the gate of PT.
sub.
11 from input terminal T.
sub.
IN and the feedback signal V.
sub.
OUT at the gate of PT.
sub.
12 from an output node ND.
sub.
12 coupled to output terminal T.
sub.
OUT.
The initial-stage differential amplifier's output at node ND.
sub.
11 is supplied to the gates of an nMOS transistor switch NT.
sub.
14 and an output stage nMOS transistor switch NT.
sub.
13.
The drain current I.
sub.
14 of NT.
sub.
14 is the control current I.
sub.
17 for a current mirror formed by pMOS transistors PT.
sub.
17 and PT.
sub.
18.
Another current mirror made of pMOS transistors PT.
sub.
15 and PT.
sub.
16 supplies the drain current of PT.
sub.
16 to output node ND.
sub.
12 connected to output terminal T.
sub.
OUT.
The pMOS transistor PT.
sub.
19 is connected as a constant-current source between supply voltage V.
sub.
DD and output node ND.
sub.
12 so that it maintains a constant idling current I.
sub.
19 into output node ND.
sub.
12.
The gate of pMOS transistor PT.
sub.
19 is connected to a constant reference voltage V.
sub.
B1.
The sources of mirror transistors PT.
sub.
17 and PT.
sub.
18 are connected to supply voltage V.
sub.
DD, their gates are connected to each other, to the drain of PT.
sub.
17 (node ND.
sub.
13), and to the drain of NT.
sub.
14.
The drains of transistors PT.
sub.
18 and PT.
sub.
15 are connected to each other to form node ND.
sub.
14, which is also connected to the gates of mirror transistors PT.
sub
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Semiconductor manufacture 
