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 PROM and ROM memory cells

Details
Inventors: Kimura, Masakazu; Kondo, Toshihiko;
Assignee: Seiko Epson Corporation (Tokyo, JP)
Primary Examiner: Crane; Sara W.
Assistant Examiner:
Attorney, Agent or Firm: Tsiang; Harold T.

An antifuse memory cell having a P.sup.+ polysilicon doping in a region directly under an intrinsic silicon programming layer. The P.sup.+ polysilicon region is surrounded by an N.sup.- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N.sup.- doping, therefore the N.sup.- polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.

DETAILED DESCRIPTION An object of the present invention is to provide an antifuse-based PROM that avoids having to compromise between low enough polysilicon doping levels to have acceptable diode diffusion currents and high enough polysilicon doping levels to have adequate conductivity for the bit line interconnects.
Another object of the present invention is to provide an antifuse-based PROM that has a narrower range of ON currents and a narrower range of OFF currents and a wider separation between ON and OFF currents in the memory cells contained within a matrix inside the PROM.
Another object of the present invention is to provide a ROM that has improved isolation diodes and that is easy to process through the final mask that contains the data to be stored.
Briefly, one embodiment of the present invention comprises an antifuse memory cell having a P.
sup.
+ polysilicon doping in a region directly under an intrinsic silicon programming layer.
The P.
sup.
+ polysilicon region is surrounded by an N.
sup.
- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation.
The interface between the two regions is a P-N junction, in fact, a diode.
The diode does not suffer from a diffusion current that increases with increasing levels of N.
sup.
- doping, therefore the N.
sup.
- polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix.
The interconnect line widths can be very narrow, and further microminiaturization is aided thereby.
The top metalization is aluminum and serves as a word line interconnect in the memory matrix.
An advantage of the present invention is that impurities in lower layer wiring layers do not migrate as far as the Schottky barrier diodes, even after heat processing.
Schottky barrier diodes having good electric properties are possible without inviting increased reverse currents (diffusion current).
A further advantage of the present invention is that an antifuse-based PROM with a large difference between ON and the OFF currents is possible, and reliability will thereby be improved



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