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Process for manufacturing discrete electronic devices
| Details |
Inventors: Igel, Gunter; Stroh, Ruediger Joachim;
Assignee: Micronas Intermetall GmbH (Freiburg, DE)
Primary Examiner: Niebling; John F.
Assistant Examiner: Jones; Josetta
Attorney, Agent or Firm: Plevy; Arthur L.
A process for manufacturing discrete electronic devices with active structures in an SOI (silicon-on-insulator) substrate which is thickened by an epitaxial layer and whose surface has a <100> orientation, said process comprising the steps of: anisotropically etching the first silicon layer to form a moat having a diameter tapering in the direction of the insulator layer, said moat extending to the insulator layer; forming an insulating layer on the sidewalls of the moat; removing a portion of the insulator layer adjoining the moat to expose a portion of the second silicon layer, which is separated from the first silicon layer by the insulator layer; forming the active structure in the second silicon layer below the portion of the insulator layer which was removed; and depositing a contact layer on the insulating layer and the active element for making contact to the active structure. |
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DETAILED DESCRIPTION OF THE INVENTION FIG.
1a shows an SOI substrate with a first silicon layer 10, an insulator layer 12, and a second silicon layer 13.
The first silicon layer 10 has been thickened by an epitaxial layer 11.
Through the epitaxial layer 11, the desired thickness of the first silicon layer 10 is achieved.
The surface of the first silicon layer has a <100> orientation.
In FIG.
1b, a masking layer 14 with an opening 15 of a predetermined width or predetermined diameter d1 has been deposited on the first silicon layer 10.
In the area of the opening 15, a truncated-cone-shaped moat or hole 16 having a sidewall 17 with a diameter tapering in the direction of the insulator layer 12 has been etched in the first silicon layer 10.
The inclination of the moat's sidewall 17 is determined by the orientation of the first silicon layer 10.
The ratio of the diameter d1 of the moat's upper opening to the diameter d2 of the moat's lower opening is thus determined by the thickness of the first silicon layer 10.
In FIG.
1c, a doped region 19 has been formed in the second silicon layer 13 below a region 18 of the insulator layer 12 adjoining the moat 16.
Doping was carried out through the insulator layer 12 wherein the moat 16 was used for masking purposes.
The doped region 19 is approximately the size of the lower diameter d2.
This requires a photolithographic technique whose spatial resolution must be just sufficient to form an opening with the upper diameter d1 of the moat 16.
The conductivity type of the doped region 19 is opposite to that of the second silicon layer 13, so that a pn junction, and thus a diode, is produced.
In FIG.
1d, the region 18 adjoining the moat 16 has been removed from the insulator layer 12, by etching, preferably anisotropic etching.
It is also possible to interchange the order of the steps performed in FIGS.
1c to 1d, so that first the region 18 is removed from the insulator layer 12 and then the doped region 19 is formed.
In FIG.
1e, the sidewall 17 of the moat 16, the sidewall created by the removal of the region 18 from the insulator layer 12, and the doped region 19 have been covered by a contact layer 20, which is generally made of metal
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