 Integrable MOS and IGBT devices having trench gate structure |
| OF ILLUSTRATIVE EMBODIMENTS FIG. 3 is a section view of a power MOSFET device in accordance with ... |
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| Insulated gate static induction transistor and integrated circuit including same |
| Therefore, an object of the present invention is to provide an insulated-gate static induction ... |
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| Mask surrogate semiconductor process employing dopant-opaque region |
| A general object of the present invention, therefore, is to provide a novel manufacturing procedure ... |
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| High speed, low gate/drain capacitance DMOS device |
| It is a purpose of the present invention to provide a new and improved method of producing high ... |
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| Method for the preparation of a pattern overlay accuracy-measuring mark |
| Therefore, it is an object of the present invention to overcome the above problems encountered in ... |
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| Power insulated-gate transistor having three terminals and a manufacturing method thereof |
| OF THE PREFERRED EMBODIMENTS FIGS. 2 illustrates the structure of an insulated-gate transistor in ... |
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| High-voltage transistor and manufacturing method therefor |
| Therefore, it is an object of the present invention to provide a high-voltage transistor which can ... |
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| Inelastic, heat-elasticizable sheet material for diapers |
| In FIG. 1, heat-shrinkable composite 10 comprises a plurality of parallel elastomeric strands, ... |
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| Disposable diaper with a repositionable tape tab fastener |
| According to the present invention, a disposable diaper is provided which has a pressure-sensitive ... |
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Raised source/drain using recess etch of polysilicon
| Details |
Inventors: Gambino, Jeffrey P.; Halle, Scott; Mandelman, Jack A.; Stephens, Jeremy K.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Nguyen; Tuan H.
Assistant Examiner:
Attorney, Agent or Firm: Scully, Scott, Murphy & Presser, Capella; Steven
A process for forming raised source/drain junctions using CMP (Chemical Mechanical Polishing) combined with a recess etch of blanket polysilicon. The raised source/drains are defined by gate conductors and by raised STI (Shallow Trench Isolation) which also reduces leakage current through the devices and improves the threshold voltage control. The process uses a salicide gate conductor, and uses conventional polysilicon deposition, CMP, and recess steps to form the raised source/drain junctions, such that it is readily implemented in commercially feasible manufacturing processes. |
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DETAILED DESCRIPTION Accordingly, it is a primary object of the present invention to provide a preferred process for making logic devices with raised source/drain junctions using recess etch of polysilicon.
A further object of the subject invention is the provision of a process for forming raised source/drain junctions using CMP (Chemical Mechanical Polishing) of blanket polysilicon combined with a recess etch.
The raised source/drains are defined by gate conductors and by raised STI (Shallow Trench Isolation).
The raised STI provides an additional benefit of reducing leakage current through the devices and improving the threshold voltage control.
The process uses a salicide gate conductor.
The disclosed process preferably uses conventional polysilicon deposition, CMP, and recess steps to form the raised source/drain junctions.
Hence, it is more readily implemented in a commercially feasible manufacturing process than previously proposed processes.
The invention further encompasses raised source/drain designs having reduced profile relative to the surrounding STI.
These and other aspects of the invention are described in further detail below with reference to the drawings.
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Semiconductor manufacture 
