Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Semiconductor manufacture Self-aligned-MOSFET-gate-source-drain-salicide-formation

 Method for forming a MOSFET with substrate source contact
Accordingly, it is an object of the present invention to provide an improved means and method for MO...


 Integrable MOS and IGBT devices having trench gate structure
OF ILLUSTRATIVE EMBODIMENTS FIG. 3 is a section view of a power MOSFET device in accordance with ...


 Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current
I claim: 1. A trench MOSFET comprising: (a) at least one pedestal, that functions as a vertically-...


 Insulated gate static induction transistor and integrated circuit including same
Therefore, an object of the present invention is to provide an insulated-gate static induction ...


 Mask surrogate semiconductor process employing dopant-opaque region
A general object of the present invention, therefore, is to provide a novel manufacturing procedure ...


 High speed, low gate/drain capacitance DMOS device
It is a purpose of the present invention to provide a new and improved method of producing high ...


 Method for the preparation of a pattern overlay accuracy-measuring mark
Therefore, it is an object of the present invention to overcome the above problems encountered in ...


 Power insulated-gate transistor having three terminals and a manufacturing method thereof
OF THE PREFERRED EMBODIMENTS FIGS. 2 illustrates the structure of an insulated-gate transistor in ...


 High-voltage transistor and manufacturing method therefor
Therefore, it is an object of the present invention to provide a high-voltage transistor which can ...


 Inelastic, heat-elasticizable sheet material for diapers
In FIG. 1, heat-shrinkable composite 10 comprises a plurality of parallel elastomeric strands, ...


 Self-aligned MOSFET gate/source/drain salicide formation

Details
Inventors: Naem, Abdalla Aly;
Assignee: National Semiconductor Corporation (Santa Clara, CA)
Primary Examiner: Niebling; John
Assistant Examiner: Lebentritt; Michael S.
Attorney, Agent or Firm: Limbach & Limbach L.L.P.

MOSFET device structure includes planarized trench isolation field oxide regions formed in a silicon substrate, a layer of gate oxide formed on the substrate to electrically insulate the polysilicon gate from the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate and the gate oxide, and LDD N-regions formed in the substrate adjacent to the field oxide regions and beneath the sidewall spacers to define a channel region in the substrate beneath the polysilicon gate. A layer of polysilicon is deposited on the above-defined structure and a chemical mechanical polishing step is performed to form raised source/drain polysilicon regions that are self-aligned to the LDD N- regions. N-type dopant is then implanted into the polysilicon gate and into the raised source/drain polysilicon regions. A first rapid thermal processing (RTP) step is then performed to activate the N-type dopant and to diffuse N-type dopant from the raised source/drain polysilicon regions into the underlying LDD N- regions to form N+ junctions within the LDD N- regions. A layer of cobalt is then deposited on the polysilicon gate and on the raised source/drain polysilicon regions in ultra high vacuum. The cobalt layer is then implanted with heavy ions to mix the cobalt and silicon at the cobalt/poly interface. A thin titanium nitride film is then formed on the cobalt layer to protect the cobalt film from nitrogen diffusion during RTP. A second RTP step is then performed to form cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate.

DETAILED DESCRIPTION The present invention provides a method of fabricating a MOSFET device structure in a silicon substrate.
The MOSFET device structure includes planarized trench isolation field oxide regions formed in the substrate, a layer of gate oxide formed on the substrate to electrically insulate the polysilicon gate from the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate and gate oxide, and LDD N- regions formed on the substrate adjacent the field oxide regions and beneath the sidewall spacers to define a channel region in the substrate beneath the polysilicon gate.
In accordance with the method of the invention, a layer of polysilicon is deposited on the abovedefined structure and a chemical mechanical polishing step is performed to define raised source/drain polysilicon regions that are self-aligned to the LDD N- regions.
N-type dopant is then implanted into the polysilicon gate and into the raised source/drain polysilicon regions.
A first rapid thermal processing step is then performed to activate the N-type dopant and to diffuse N-type dopant from the raised source/drain polysilicon regions into the underlying LDD N- regions to form shallow N+ junctions within the LDD N- regions.
A cleaning step is performed and a layer of cobalt is then deposited on the polysilicon gate and on the raised source/drain polysilicon regions.
The cobalt layer is then implanted with heavy ions to mix the cobalt and silicon at the interface of the cobalt layer and the underlying polysilicon.
A titanium nitride capping film is then formed on the cobalt layer to protect the film from nitrogen diffusion during RTP, which results in producing a highly uniform salicide layer due to the absence of foreign materials in the cobalt film.
The TiN film also results in reducing the RTP thermal budget.
The first salicidation RTP step is performed at low temperature (about 450 degrees C.
) to allow the cobalt to be the diffusing species into the underlying silicon.
By doing this, the lateral growth of the cobalt salicide is eliminated



Related patents
  Raised source/drain using recess etch of polysilicon
Accordingly, it is a primary object of the present invention to provide a preferred process for making logic devices with raised source/drain junctions using recess etch ...
  Method of producing a metal oxide semiconductor device with raised source/drain
There is a need for a method of making a semiconductor device with raised source/drain structure, in a readily manufacturable process that is cost effective. This and ...
  Method for forming shallow source/drain extension for MOS transistor
OF THE INVENTION". BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of a semiconductor device made according to the present invention, shown in combination ...
  Laser texturing
The present invention is directed to providing a contactless technique for imparting a texture to a surface by promoting a chemical etching reaction between a gaseous ...
  Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
FIG. 2 shows a trenched DMOS transistor structure in accordance with the present invention. The substrate (drain) region 10 is in the lower portion of the semiconductor ...
  Semiconductor device and power converter using same
The semiconductor device according to the present invention has a pair of main surfaces. On one main surface side, the surface of a first semiconductor region of a first ...
  Self-aligned channel stop for trench-isolated island
In accordance with the present invention, the need to provide a separation region between the trench and a device region within the island, which results in an unwanted ...
  DMOS power transistors with reduced number of contacts using integrated body-source connections
In accordance with the present invention, two topologically different microcells are provided. Each of these microcells is designed to reduce the total number of ...
  Trench depletion MOSFET
The present invention is a trench power MOSFET with a unique structure which overcomes the above-noted deficiencies of the prior art. Advantageously, the present ...
  ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST*** *** NO IMAGES AVAILABLE***
Description:...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved