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Topography for integrated circuit operational amplifier having low impedance input for current feedback
| Details |
Inventors: Halbert, Joel M.; Murray, Kenneth W.; Yuan, Dan;
Assignee: Burr-Brown Corporation (Tucson, AZ)
Primary Examiner: Mullins; James B.
Assistant Examiner:
Attorney, Agent or Firm: Cahill, Sutton & Thomas P.L.C.
A high speed integrated circuit operational amplifier chip first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. The most thermally sensitive transistors are disposed along or symmetrically about the thermal centerline to provide approximately balanced response by such transistors to differential heating by the output driver circuit. The bonding pads, which function as heat sinks, also are symmetrically disposed on or about the thermal centerline. |
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DETAILED DESCRIPTION Accordingly, it is an object of the invention to provide an integrated circuit chip topography for a high speed amplifier with a low impedance input to allow use of current feedback, and more particularly to such a topography which occupies a minimum amount of chip area and avoids performance degradation due to unbalanced internal thermal responses of thermally sensitive transistors to internal heat generation.
Briefly described, and in accordance with one embodiment thereof, the invention provides a high speed integrated circuit operational amplifier chip (60) including first (60L), second (60B), third (60R) and fourth (60T) successive edges.
The operational amplifier chip includes a plurality of bonding pads, including an inverting input bonding pad (62B) located in a first corner formed by the first (60L) and fourth (60T) edges, a non-inverting input bonding pad (62A) located in a second corner formed by the first (60L) and second (60B) edges, a V.
sub.
EE bonding pad located in a third corner formed by the second (60B) and third (60R) edges, a V.
sub.
CC bonding pad located in a fourth corner formed by the third (60L) and fourth (60T) edges, and an output bonding pad located along the third edge (60R) between the V.
sub.
EE and V.
sub.
CC bonding pads.
A thermal centerline (44) parallel to the second and fourth edges divides the chip into approximately equal sections.
An output driver circuit (68) is located adjacent to the output bonding pads and is disposed approximately symmetrically about the thermal centerline (44) to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline.
A low gain differential input circuit (66) is located adjacent to the first edge (60L) and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating.
PNP current mirror transistors (5, 6, 7) are located in a first area (67) adjacent to the low gain differential input circuit (66) and are symmetrically disposed about the thermal centerline (44)
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Semiconductor manufacture 
