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Trench depletion MOSFET
| Details |
Inventors: Ajit, Janardhanan S.;
Assignee: International Rectifier Corporation (El Segundo, CA)
Primary Examiner: Loke; Steven H.
Assistant Examiner:
Attorney, Agent or Firm: Ostrolend, Faber, Gerb & Soffen, LLP
A vertical trench power MOS transistor with low on-resistance is obtained by eliminating the inversion region of a conventional structure. In one embodiment, a deep-depletion region is formed between the trench gates to provide forward blocking capability. In another embodiment, forward blocking is achieved by depletion from the trench gates and a junction depletion from a P diffusion between the gates. Both embodiments are preferably fabricated in a cellular geometry. The device may also be provided in a horizontal conduction configuration in which the MOS gate is disposed on the upper surface of the semiconductor wafer over the deep-depletion region. |
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DETAILED DESCRIPTION The present invention is a trench power MOSFET with a unique structure which overcomes the above-noted deficiencies of the prior art. Advantageously, the present invention, like the trench power MOSFET of FIG. 2, does not have a P base region and thus has no P-N junction. Thus, the trench power MOSFET of the present invention is formed in a wafer of semiconductor material having first and second (i. e. upper and lower) opposing semiconductor surfaces, the wafer of semiconductor material including a relatively lightly doped region of a first conductivity type, preferably N. sup. -, a plurality of spaced narrow trenches perpendicularly formed in the wafer and extending from the upper surface of the wafer, at least a portion of the N. sup. - region being disposed between the trenches from the upper semiconductor surface. Polysilicon gates are disposed in the trenches and spaced from the intervening portion of the N. sup. - region by a layer of gate insulation material. A first relatively highly doped region of the first conductivity type, i. e. N. sup. +, is disposed between and adjacent to the upper semiconductor surface and the N. sup. - region. The present invention is an improvement over the prior art device of FIG. 2, however, by the inclusion, in a first embodiment, of a P. sup. + region formed in the wafer and extending from the upper surface of the wafer at a position adjacent to and at least partially co-extensive with the upper N. sup. + region, i. e. the source region. On application of a negative gate voltage to turn the device off, the added P. sup. + region forms a drain for holes generated in the N. sup. - region. Thus, as soon as the holes are formed, they are swept off towards the P. sup. + region by the electric field, via a trench p-channel MOSFET. This effect is hereinafter termed "deep-depletion. " The deep-depletion very efficiently pinches off the N. sup. - region between the trench MOS gates, forming a potential barrier to the flow of electrons and greatly improving the forward blocking capability of the device
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