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Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
| Details |
Inventors: Hshieh, Fwu-Iuan; Chang, Mike F.; Ching, Lih-Ying; Ng, Sze H.; Cook, William;
Assignee: Siliconix incorporated (Santa Clara, CA)
Primary Examiner: Crane; Sara W.
Assistant Examiner: Hardy; David B.
Attorney, Agent or Firm:
A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced. |
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DETAILED DESCRIPTION FIG. 2 shows a trenched DMOS transistor structure in accordance with the present invention. The substrate (drain) region 10 is in the lower portion of the semiconductor body and is N+ doped (in this N-channel embodiment) to have a resistivity in the range of 1 milliohm to 5 milliohms, i. e. 1. 5. times. 10. sup. 19 to 7. 5. times. 10. sup. 19 /cm. sup. 3. A typical thickness of drain region 10 is 400 . mu. m. Overlying drain region 10 is an N- doped drift region 14 doped to a level of 3. times. 10. sup. 19 to 3. times. 10. sup. 16 /cm. sup. 3. Formed between the drift region 10 and the drain region 14 are buried layer regions 16 which are N+ (or N++) doped. Each buried layer region has a doping level exceeding that of the drift region 14 and in one embodiment approximately 3 to 10 times the doping level of the drain region 10. Typically the buried layer regions 16 are arsenic or phosphorous or POCl. sub. 3 doped. Each buried layer region 16 is e. g. 1 to 2 . mu. m wide (depending on the process technology) and has a height in a range of e. g. 0. 5 to 2. 0 . mu. m. (It is to be understood that the various dimensions and parameters given herein are illustrative and not limiting. ) As can be seen, the buried layer regions 16 are located in the lower portion of the drift region 14 and in the upper portion of the drain region 10. Overlying drift region 14 is a P doped body region 18 having a thickness of e. g. 12 . mu. m and a doping concentration of e. g. 5. times. 10. sup. 16 /cm. sup. 3. Formed in body region 18 are conventional N+ source regions 20 having a doping level of e. g. 5. times. 10. sup. 19 /cm. sup. 3 and a depth of e. g. 0. 5 . mu. m and a width of e. g. 2 . mu. m. Also formed in the P doped body region 18 are P+ doped body contact regions 24 having a doping level of e. g. 10. sup. 19 /cm. sup. 3 and a depth of e. g. 1. 0 . mu. m. These P+ doped regions 24 provide electrical contact to the underlying P body region 18 for the overlying metalization layer 44. It is to be understood that while P+ body contact regions 24 are depicted as deep body regions extending into drift region 14, regions 24 may be shallower, in which case the breakdown current conduction path is from body region 18 to buried layer 16
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