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Apparatus and method of transferring video data of a moving picture
| Details |
Inventors: Takeuchi, Kesatoshi;
Assignee: Seiko Epson Corporation (Tokyo-to, JP)
Primary Examiner: Kostak; Victor R.
Assistant Examiner: Flynn; Nathan J.
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
A multiplier 7 multiplies an adding address stored in an adding address memory 3 by a vertical count output from a vertical counter unit 4. A first adder 8 adds the product of the multiplier 7 to an offset address stored in the offset address memory 2. A second adder 9 adds the sum in the first adder 8 to a horizontal count in a horizontal counter unit 5. A third adder 10 adds the sum in the second adder 9 to each of area-start addresses for RGB color components stored in three area-start address memory units 6R, 6G, and 6B, respectively. An output AD3 from the third adder 10 becomes an access address in DMA transfer. The access address in DMA transfer is accordingly calculated by simple arithmetic operation in a DMA controller 34, which thereby attains high-speed DMA transfer. |
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DETAILED DESCRIPTION An object of the present invention is to execute a high-speed transfer of video data to a VRAM to thereby display a smooth moving picture.
The present invention is directed to an apparatus, for use in a computer system comprising a processor for performing logical operation and a video memory controlled by the processor for storing video data, for transferring moving-picture video data representing a moving picture to a desirable memory area in the video memory, comprising: a first memory for storing an offset address indicating a start position of the desirable memory area in the video memory; a second memory for storing an adding address indicating a difference between addresses of two scanning lines adjacent to each other in the video memory; first operation means for calculating a vertical address as a function of vertical and horizontal synchronizing signals synchronous with the moving-picture video data, the vertical address being equal to a value of the adding address multiplied by a scanning line number indicating an ordinal number of a scanning line in the moving picture, the scanning line number being specified by the number of pulses of the horizontal synchronizing signal given to the first operation means; a horizontal counter for generating a horizontal address indicating a difference of an address between an initial position of each scanning line in the moving picture and each pixel on the each scanning line; second operation means for adding the vertical address, the horizontal address, and the offset address to obtain a transfer address indicating an address in the video memory corresponding to a position of the each pixel on the each scanning line in the moving picture, and outputting the transfer address onto an address bus connected to the video memory; and data output means for outputting the moving-picture video data to be transferred to the video memory according to the transfer address, onto a data bus connected with the video memory.
Since the transfer address is calculated by arithmetic operation in the first and second operation means, the transfer address can be computed at a high speed
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