Channel selector employing variable capacitance elements for tuning

DETAILED DESCRIPTION What is claimed is: 1.
A television receiver channel selector for selecting one from among a plurality of channel tuning frequencies, comprising: a tuning circuit tunable to said plurality of channel tuning frequencies, including variable capacitance diodes as tuning elements; a plurality of voltage supply circuits for supplying at outputs thereof tuning voltages corresponding to said plurality of channel tuning frequencies; binary memory circuit means having a plurality of outputs for producing binary coded information signals corresponding to said channel tuning frequencies, said memory circuit comprising a binary counter circuit having a plurality of complementary pairs of output terminals; binary decoder means having a plurality of complementary pairs of input terminals connected to said counter circuit output terminals and a further plurality of terminals coupled to the outputs of said voltage supply circuits; means for selectively connecting the outputs of said voltage supply circuits to said variable capacitance diodes for tuning said tuning circuit to one of said channel tuning frequencies, including means selectively connecting the output of one of said voltage supply circuits to said variable capacitance diodes to tune said tuning circuit to the corresponding channel tuning frequency and disconnecting the outputs of all others of said voltage supply circuits from said variable capacitance diodes, the selective connection of said one voltage supply circuit and disconnection of said all other voltage supply circuits being controlled by a given binary decoder means output; a pulse generator circuit coupled to an input of said binary counter circuit for supplying pulses in sequence to said counter circuit and switch means for controlling the supply of pulses from said pulse generator to said counter circuit; and reversing switch means interposed between each set of corresponding pairs of said input and output terminals of said decoder and counter circuit, respectively, for reversing the connections between said input and output terminals within each set of said corresponding pairs of terminals