Clock generation circuit for multistandard serial digital video with automatic format identification

DETAILED DESCRIPTION It is an object of the present invention to provide a method and circuit for producing frequency agile clock signals suitable for use with D1 component digital video, NTSC and PAL D2 composite digital video signals, and a proposed new standard video format that uses a 360 MHz clock signal.
A voltage controlled reference oscillator with a high Q and narrow tunability bandwidth produces an output oscillator frequency which is frequency divided by four alternative constants to produce the four different clock frequencies for the four digital video standards, D1 component at 270 MHz, NTSC D2 composite at 143 MHz, PAL D2 composite at 177 MHz, and a proposed new component video standard that is to operate at a 360 MHz clock rate.
It is also an object of the present invention to be able to automatically identify which video standard is present and produce the appropriate clock signal accordingly.
A clock generator is made to produce a clock signal at the frequency required by one of the video formats, and a phase lock loop attempts to lock onto the incoming signals at that frequency.
If no lock occurs within a predetermined time interval, the clock generator is made to produce a clock signal at the frequency required by a different one of the video formats and the phase lock is attempted again.
This is repeated until a lock occurs.
Optionally, when a lock is achieved, the video is tested for validity within the format that is consistent with the standard associated with the clock frequency that produced the lock.
The subject matter of the present invention is particularly pointed out and distinctly claimed in the concluding portion of this specification.
However, both the organization and method of operation, together with further advantages and objects thereof, may best be understood by reference to the following detailed description and accompanying drawings.