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 Digital selective calling receiver having a selectively attachable device for multiple independent address decoding capability

Details
Inventors: Davis, Walter L.;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Yusko; Donald J.
Assistant Examiner: Pudpud; E. O.
Attorney, Agent or Firm: Zitelli; William E., Ingrassia; Vincent B.

A digital selective call receiver is modified to enhance the address decoding capability by providing access to received data, bit and frame synchronization signals, and a detect input terminal of an annunciator. A selectively attachable additional independent address decoding device including additional memory and an independent address decoder operating in parallel with the decoder in the selective call receiver is attached to the receiver for accessing the various signals and providing a detect signal to the annunicator when an additional independent address is decoded.

DETAILED DESCRIPTION I claim: 1.
In a digital selective call receiver including a receiver circuit for receiving transmitted signals, and a decoder for decoding said received signals, said decoder comprising: a memory containing a digital sequence corresponding to one address of the receiver; means for generating bit and frame synchronization signals; a comparator coupled to the receiver circuit and memory and governed by the bit and frame synchronization signals to determine correspondence between the receiver signals and the digital sequence stored in said memory; and annunciator responsive to the comparator for alerting the user of such correspondence which is indicative of the reception of a selective call message, a selectively attachable additional independent address decoding device comprising: additional memory means containing at least one additional independent digital sequence address; and additional decoder means operative in parallel with said decoder for independently decoding received signals including additional comparator means coupled between the receiver circuit and said additional memory means, and governed by the bit and frame synchronization signals of the decoder to determine correspondence between the received signals and the additional independent digital sequence address, and for providing a separate signal to the annunciator for alerting the user of such correspondence which is indicative of the reception of a selective call message corresponding to the at least one additional independent digital sequence address.
2.
The selectively attachable decoding device of claim 1 wherein the additional memory means is contiguous with said memory.
3.
The selectively attachable decoding device of claim 1 further including means for generating an additional signal and providing said signal to said annunciation means to distinguish the detection of at least one additional independent address.
4.
The selectively attachable decoding device of claim 3 wherein said decoder further includes means to detect the reception of functional code words which are not independent of the additional independent address and supply signals representative of the detected functional code words to the annunciator



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