Interface for a video display processor arranged to provide an overlay on a video display

DETAILED DESCRIPTION The foregoing and additional objects are achieved in accordance with the present invention by an interface circuit designed for connection between a source of video signals such as a video disc player and a video display processor arranged to overlay a picture with graphics.
The interface includes (a) a video matching/sync stripper circuit for referencing the video signal to the levels generated by the VDP and for extracting the sync signal from the video input, (b) a phase-locked loop responsive to the extracted sync signal for deriving both a clock signal for the VDP clock input as well as a horizontal sync signal for the VDP sync input, and (c) a sync circuit including a low-pass filter and a vertical sync generator for deriving a vertical sync signal from the extracted sync information.
If required, a summer may be used to combine the separate vertical and horizontal sync signals into a composite sync signal which is applied to the VDP.
A color subcarrier regenerator may also be included in the interface circuit.