Jitter correction circuit

DETAILED DESCRIPTION A primary object of the present invention is to provide a jitter correction circuit of a relatively simple configuration for suppressing a jitter.
According to an embodiment of the invention a jitter correction circuit comprises a first oscillation control circuit for providing a first oscillation output having a rapid frequency response characteristic according to phase deviation in a reproduced horizontal synchronizing signal; an analog-to-digital converting circuit for sampling the reproduced video signal based on the first oscillation output to provide digitally converted data; a second oscillation control circuit for providing a second oscillation output having a stable frequency response characteristic according to the phase deviation in the reproduced horizontal synchronizing signal or phase deviation in the first oscillation output; and resampling circuit for resampling the digitally converted data based on the second oscillation output.
Consequently, according to the above described embodiment of the invention, the reproduced video signal containing a jitter component is converted to digital data based on the first oscillation output containing a jitter component and the digital data thus obtained by analog-to-digital conversion is resampled based on the second oscillation output containing little jitter component.
According to another embodiment of the invention, a jitter correction circuit comprises: a serial-to-parallel converting circuit for reading digital data in synchronism with the first clock following a jitter so as to latch the data converted from serial data to parallel data in synchronism with a 1/n frequency divided pulse of the first clock; and a parallel-to-serial converting circuit for latching again the above stated latched parallel data in synchronism with a 1/n frequency divided pulse of the stable second clock so as to convert the parallel data to serial data based on the above stated second clock.
Consequently, according to the above described latter embodiment of the invention, a period for transferring data to the parallel-to-serial converting circuit can be made n times as long by the serial-to-parallel conversion and a jitter correction amount can be made n times as much