Phase-lock-loop lock indicator circuit

DETAILED DESCRIPTION OF THE INVENTION Referring to FIG.
1, a block diagram illustrating a phase-lock-loop including the phase-lock-loop lock indicator circuit 10 of the present invention is shown comprising phase/frequency detector 2 having a first input coupled to input terminal 4 and a second input coupled to an output of voltage controlled oscillator (VCO) 6.
The first output of phase/frequency detector 2 is coupled to a first input of loop filter 8 and to a first input of phase-lock-loop (PLL) lock indicator circuit 10 while the second output of phase/frequency detector 2 is coupled to a second input of loop filter 8 and to a second input of phase-lock-loop (PLL) lock indicator circuit 10.
The output of loop filter 8 is coupled to an input of VCO 6 while and output of PLL lock indicator circuit 10 is coupled to output terminal 11.
It should be known by one of ordinary skill in the art that the phase-lock-loop circuit comprises phase/frequency detector 2, loop filter 8 and VCO 6.
Briefly, phase/frequency detector 2 compares the input reference signal with the output signal of VCO 6 and provides UP and DOWN output signals.
If the VCO output signal is at a lower frequency than the input reference signal, then the UP signal will be in a first logic state thereby increasing the output frequency of the VCO.
Likewise, if the VCO output signal is at a higher frequency than the input reference signal, then the DOWN signal will be in a first logic state thereby decreasing the output frequency of the VCO.
When both the UP and DOWN signals are in a second logic state, the VCO output signal is substantially the same phase and frequency of the input reference signal.
PLL lock indicator circuit 10 is responsive to the UP and DOWN signals being in a second logic state by providing output logic signal LOCK at output terminal 11.
Referring to FIG.
2, the phase-lock-loop lock indicator circuit 10 of the present invention is shown comprising digital filters 12 and 14 having inputs coupled to input terminals 16 and 18, respectively