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 Phase shifter control circuit

Details
Inventors: Bock, Ditmar H.;
Assignee: Calspan Corporation (Buffalo, NY)
Primary Examiner: Smith; Alfred E.
Assistant Examiner: Grigsby; T. N.
Attorney, Agent or Firm: Biebel, French & Nauman

A phase shifter control circuit having an integrator circuit for developing as a phase control signal the time integral of an input command or error signal, a reset circuit responsive to the phase control signal for generating a correction signal whenever the phase control signal reaches predetermined limits, and summing circuits for combining the correction signal with the input signal and with the phase control signal whereby the phase control signal is substantially instantaneously adjusted to a value between the predetermined limits.

DETAILED DESCRIPTION The foregoing difficulties are overcome according to the teachings of the present invention which provides a phase shift circuit controller permitting substantially instantaneous phase shifts in response to either a command signal or an error signal.
Essentially, the present invention provides a novel circuit for generating the applied phase controlling voltage in such a manner that whenever such voltage nears predetermined limits, usually upper or lower limits, signals are developed which, when combined with the normal input to such circuit, deliver a phase controlling voltage that is substantially instantaneously at the desired value; to thereby eliminate transitions through intermediate values.
An integrating circuit is provided to accommodate the normal fluctuations of the phase controlling voltage between the chosen predetermined limits; however, when the voltage reaches such limits a reset circuit is actuated which delivers a correction signal that when combined with the normal input signal to the integrator circuit and the output therefrom results in a phase controlling voltage that is immediately at the desired value.
Basically, then, the present invention provides a phase shifter control circuit, comprising; a first summing circuit for combining a normal input signal with a correction signal to produce an output signal representing the sum thereof, an integrator circuit responsive to such output signal for developing an integrated signal representing the time integral thereof and a second summing circuit for combining the integrated signal with the correction signal.



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