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Shift register
| Details |
Inventors: Yamada, Kunihiro;
Assignee: Ricoh Company, Ltd. (Tokyo, JP)
Primary Examiner: Popek; Joseph A.
Assistant Examiner:
Attorney, Agent or Firm: Oblon, Fisher, Spivak, McClelland & Maier
A shift register of the type capable of performing shift operations by changing the access of a random access memory, which is capable of performing the operations at a high speed, with respect to the address for reading data and the output of a counter, the input to which is a clock pulse. In order to increase the operations of the shift register, the operation of the address is performed in a power form or each input data is written at two different addresses of the random access memory. |
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DETAILED DESCRIPTION It is therefore an object of the present invention to provide a shift register which is made simple in mechanism and inexpensive by use of a RAM of great capacity and which is capable of performing high speed operations and stopping the supply of clocks, and from which the above-described drawbacks in the prior-art shift registers have been successfully eliminated. In order to attain this object, an embodiment of a shift register according to the present invention comprises a Random Access Memory (RAM) with a capacity of more than 2. sup. k words, a k-bit counter which is counted down each time a clock pulse is input thereto and designates an address of the RAM in accordance with the counted value, at which address an input data is written, and an operation unit for adding the address indicated by the k-bit counter to the address of the shifted data to be read, making the added address the address of the data to be read by the RAM, thereby outputting the data which has been shifted by the number of steps corresponding to the number of clock pulses applied by that time, when a clock pulse is not input to the shift register. Furthermore, in order to attain the above-mentioned object, another embodiment of a shift register according to the present invention comprises a RAM with a capacity of more than 2n words, a counter, an operation unit, a constant generation apparatus and a sequence control apparatus. In this embodiment, when a clock pulse is input thereto, a constant 0 and a constant n are generated by the constant generation apparatus under the control of the sequence control signal generation apparatus, and the output of the counter and the constants are operated by the operation device, preparing their respective addresses for writing the input data in the RAM. When a clock pulse is not input to the shift register, the constant is not generated by the constant generation apparatus, and the address of the shifted data is input to the operation unit as it is, thereby preparing the address for reading the shifted data from the RAM
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