Thin film resistor and method for producing same

DETAILED DESCRIPTION OF THE INVENTION FIG.
1 is the schematic view of a semiconductor structure with a resistor mounted thereon that has been trimmed in accordance with the invention.
It should be noted that FIG.
1 is not drawn to scale.
The semiconductor structure comprises a silicon masterslice 10 that includes a multiplicity of active devices formed therein (not shown).
A pair of personalization layers 12 and 14 are emplaced on the surface of masterslice 10 and perform the function of interconnecting various of the devices in the masterslice, in the well known manner.
Personalization layer 12 comprises a metallization layer 16 which includes metal conductors that interconnect the various semiconductors in masterslice 10.
Disposed over metallization layer 16 is an SiO.
sub.
2 passivating layer 18 on which a nitride layer 20 is deposited.
An additional personalization layer 14 includes a further metallization layer 22, SiO.
sub.
2 layer 24 and nitride layer 26.
Disposed on nitride layer 26 is a thin film planar resistor 28 which interfaces at either of its extremities with conductive contacts 30 and 32.
Contacts 30 and 32 are connected via conductive lines (not shown) to one or more personalization layers 12 and 14 to enable resistor 28 to interconnect to various of the devices in silicon masterslice 10.
Of course, a plurality of resistors 28 will generally be present on nitride layer 26 and only one is shown for exemplary purposes.
A passivating SiO.
sub.
2 layer 34 is emplaced over contacts 30, 32 and resistor 28.
In the production process, it is often the case that resistor 28 needs to be trimmed to adjust its resistance value, so that the semiconductor circuit exhibits proper operating characteristics.
If the trim occurs prior to all processing steps being completed, the resistance and/or other circuit parameters may shift during subsequent steps, notwithstanding the trim action.
Thus, it is most desirable that the trim operation take place in the final phases of the chip and/or device process so that device operation can be adjusted to the appropriate specifications