Video signal processor for removing a separated signal component from an input video signal

DETAILED DESCRIPTION Accordingly, it is an object of the present invention to eliminate the above-described problems in the related art and to provide a video signal processor which is capable of reducing color edging, dot disturbance, cross color and deterioration in vertical resolution.
To achieve this aim, a video signal processor according to the present invention has a delay circuit for delaying an input video signal by an integral number of times the horizontal line period so as to generate two kinds of delay signals, namely, a first delay signal and a second delay signal.
The video signal processor has the following structure so as to compare these three signals.
In the first aspect of the present invention, the video signal processor comprises: a maximum value calculator for comparing the video signal, the first delay signal and the second delay signal which are input thereto and outputting the maximum value; a minimum value calculator for comparing the video signal, the first delay signal and the second delay signal which are input thereto and outputting the minimum value; a synthesizer for outputting a signal obtained by subtracting the outputs of the maximum value calculator and the minimum value calculator from the sum of the video signal, the doubled first delay signal and the second delay signal; and a subtractor for subtracting the output of the synthesizer from the first delay signal.
In the second aspect of the present invention, the video signal processor comprises: a first synthesizer for compounding the antiphase video signal, the first delay signal and the second delay signal; a second synthesizer for compounding the video signal and the second delay signal; a third synthesizer for compounding the video signal, the doubled first delay signal and the antiphase second delay signal; a maximum value calculator for comparing the output signals of the first, second and third synthesizers which are input thereto and outputting the maximum value; a minimum value calculator for comparing the output signals of the first, second and third synthesizers which are input thereto and outputting the minimum value; an adder for adding the output of the maximum value calculator and the output of the minimum value calculator; and a subtractor for subtracting the output signal of the adder from the first delay signal