Accelerated test apparatus and support logic for a content addressable memory

DETAILED DESCRIPTION Accordingly, it is an object of the present invention to provide hardware and algorithms for testing CAMs.
Another object of the invention is to provide a means and algorithm for testing CAMs that has a minimum number of steps and operations.
Still another object of the present invention is to provide test algorithms and mechanisms for thoroughly testing all aspects of the memory cells without appreciably adding to the overhead of the CAM.
Yet another object of the invention is to provide algorithms and means for testing CAMs that may be applied to any kind of CAM.
It is another object of the present invention to facilitate a high degree of parallelism in the testing of CAM arrays.
In carrying out these and other objects of the invention, there is provided, in one form, a CAM array having n entries of m bits per entry, a word line and a match line for each wherein the match line has a state, x m bit cells each having a word line, a match line a bit line and a complementary bit line.
Each bit cell also has a memory element and an exclusive OR comparator of the cell's bit value with a value presented on the bit lines.
In addition, there is a HIT/MISS* means for ORing the states of the n match lines.
The improvement comprises an ALLHIT means separate from the HIT/MISS* means for monitoring the states of the n match lines.
The ALLHIT means also performs an operation with the states from the n match lines and provides an output signal giving the result of the operation.
The ALLHIT means may be an AND gate or a scan path.
The ALLHIT mean is for determining in one step whether all n match lines tested true.