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 Array device for data scrambling

Details
Inventors: Fleisher, Harold; Hong, Se J.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Birmiel; Howard A.
Assistant Examiner:
Attorney, Agent or Firm: Murray; James E.

This specification describes an array logic chip that can be used to encipher and decipher binary data. The array logic chip contains a matrix of input and output lines with the input lines divided into groups that are each addressed by a different decoder. The digits of a block of data to be encoded are arranged in sets according to the position of the digits in the block and a different set of digits is fed into each of the decoders of the array logic chip. Substitution of new digits for the original digits in each set is accomplished in the matrix by configuration of connections between a group of input lines and output lines of the arrays and in the decoders by changing the configuration of the decoders so as to vary the input lines of the matrix selected by the input signals to the decoders. Transposition or changing of position of the digits in the block of data is accomplished in the selection of the output lines to which any given group of input lines is connected. Multiple substitutions and transpositions are accomplished by readdressing the decoders with the coded data signals on the output lines of the matrix and dynamic encoding is accomplished by continuously reconfiguring the decoders and changing the couplings between input and output lines of the matrix.

DETAILED DESCRIPTION OF THE INVENTION FIG.
1 shows an array 10 of intersecting input and output lines 12 and 14 with each group of four input lines 12 addressed by a different 2-bit decoder 15.
As shown in FIG.
2, an AND gate 16 is located at each intersection 18 of an input and output line of the array 10.
In any particular row of AND gates in the array each AND gate receives one input from a common input line 12 and another input from a different stage 20 of a feedback shift register 22 associated with the particular input line of the array.
The output of the AND gate 16 is fed to the output line 18 passing through the intersection.
Therefore the data in the shift register controls the coupling between an input and output line of the array.
When a binary 1 is stored in any stage 20a of the shift register 22 a signal placed on the input line 12 is reproduced on the output line 18a fed by the AND gate 16a.
Otherwise the signal on the input line is masked from the output line.
The signals placed on the input lines 12 are controlled by the decoders 15 one of which is shown in detail in FIG.
3.
The inputs A and B of the decoder are each an input to two different Exclusive OR circuits 24 and 26.
The other input to the Exclusive OR circuit 24 and 26 is one of the stages 28 or 30 of a two-position register.
Either the true or inverted outputs of the Exclusive OR circuits are each fed to four AND circuits 32, 34, 36 and 38 so that depending on the input signals and the data in the shift registers one of the four output lines will be selected by the decoder.
If a binary 0 is stored in both stages 28 and 30 of the register, the first line 12a will be selected when both inputs A and B are binary 0, the second line 12b will be selected when A is a binary 1 and B is a binary 0, the third line 12c will be selected when A is a binary 0 and B is a binary 1 and the last line 12d will be selected when both inputs A and B are binary 1.
Of course as the data in stages 28 and 30 changes the line selected by the inputs A and B will also change



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