Color image data processing device featuring ghost elimination

DETAILED DESCRIPTION OF THE INVENTION FIG.
3 shows a color image data processing device used in a reading device adapted to read red and black.
The reading device receives a black signal (color signal) 11 and a red signal (color signal) 12 from a color separation circuit, or generating means (not shown).
The black signal 11 represents black for a picture element when it is at a logic level "1" (hereinafter referred to merely as "1", when applicable) and represents white when it is at a logic level "0" (hereinafter referred to merely as "0", when applicable).
The red signal 12 represents red for a picture element when it is at "1", and white when it is at "0".
The black signal 11 is applied to a first 5-bit shift register 13, and is delayed one line by a first random access memory 14.
The black signal (15) thus delayed is supplied to a second 5-bit shift register 16 and is further delayed one line by a second random access memory 17.
The black signal (18) which has been delayed two lines is applied to a third 5-bit shift register 19.
The red signal 12 is supplied to a fourth 5-bit shift register 21 and is delayed one line by a third random access memory 22.
The red signal (23) thus delayed is applied to a fifth 5-bit shift register 24 and is further delayed one line by a fourth random access memory 25.
The red signal (26) which has been delayed two lines is supplied to a sixth 5-bit shift register 27.
A clock signal 28 having a predetermined frequency is applied to the shift registers 13, 16, 19, 21, 24 and 27.
In synchronization with the clock signal 28, the shift registers provide signals 31-0 through 31-9 and 32-0 through 32-9 at parallel signal output terminals thereof, which are supplied to input terminal groups T1 and T2 of a selector 33.
In the selector 33, the signals applied to the input terminal groups T1 and T2 are selectively outputted through an output terminal group T4 in response to the state of a signal applied to a select terminal T3.
That is, when a select signal 34 whose period is one half of that of the clock signal 28 is at a high logic level (hereinafter referred to merely as "H", when applicable), the signals 31-0 through 31-9 inputted through the input terminal group T1 are outputted through the output terminal group T4